4 * Copyright (c) 2001 ARM Ltd
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * V3 V360EPI Local Bus <-> PCI bridge.
37 #define V360_PCI_VENDOR 0x00
38 #define V360_PCI_DEVICE 0x02
39 #define V360_PCI_CMD 0x04
40 #define V360_PCI_STAT 0x06
41 #define V360_PCI_CC_REV 0x08
42 #define V360_PCI_HDR_CFG 0x0c
43 #define V360_PCI_IO_BASE 0x10
44 #define V360_PCI_BASE0 0x14
45 #define V360_PCI_BASE1 0x18
46 #define V360_PCI_SUB_VENDOR 0x2c
47 #define V360_PCI_SUB_ID 0x2e
48 #define V360_PCI_ROM 0x30
49 #define V360_PCI_BPARAM 0x3c
50 #define V360_PCI_MAP0 0x40
51 #define V360_PCI_MAP1 0x44
52 #define V360_PCI_INT_STAT 0x48
53 #define V360_PCI_INT_CFG 0x4c
55 #define V360_LB_BASE0 0x54
56 #define V360_LB_BASE1 0x58
57 #define V360_LB_MAP0 0x5e
58 #define V360_LB_MAP1 0x62
59 #define V360_LB_BASE2 0x64
60 #define V360_LB_MAP2 0x66
61 #define V360_LB_SIZE 0x68
62 #define V360_LB_IO_BASE 0x6e
64 #define V360_FIFO_CFG 0x70
65 #define V360_FIFO_PRIORITY 0x72
66 #define V360_FIFO_STAT 0x74
68 #define V360_LB_ISTAT 0x76
69 #define V360_LB_IMASK 0x77
71 #define V360_SYSTEM 0x78
73 #define V360_LB_CFG 0x7a
75 #define V360_PCI_CFG 0x7c
77 #define V360_DMA_PCI_ADDR0 0x80
78 #define V360_DMA_LOCAL_ADDR0 0x84
79 #define V360_DMA_LENGTH0 0x88
80 #define V360_DMA_CSR0 0x8b
81 #define V360_DMA_CTLB_ADDR0 0x8c
83 #define V360_DMA_PCI_ADDR1 0x90
84 #define V360_DMA_LOCAL_ADDR1 0x94
85 #define V360_DMA_LENGTH1 0x98
86 #define V360_DMA_CSR1 0x9b
87 #define V360_DMA_CTLB_ADDR1 0x9c
89 #define V360_MAIL_DATA0 0xc0
90 #define V360_MAIL_DATA1 0xc1
91 #define V360_MAIL_DATA2 0xc2
92 #define V360_MAIL_DATA3 0xc3
93 #define V360_MAIL_DATA4 0xc4
94 #define V360_MAIL_DATA5 0xc5
95 #define V360_MAIL_DATA6 0xc6
96 #define V360_MAIL_DATA7 0xc7
97 #define V360_MAIL_DATA8 0xc8
98 #define V360_MAIL_DATA9 0xc9
99 #define V360_MAIL_DATA10 0xca
100 #define V360_MAIL_DATA11 0xcb
101 #define V360_MAIL_DATA12 0xcc
102 #define V360_MAIL_DATA13 0xcd
103 #define V360_MAIL_DATA14 0xce
104 #define V360_MAIL_DATA15 0xcf
106 #define V360_PCI_MAIL_IEWR 0xd0
107 #define V360_PCI_MAIL_IERD 0xd2
108 #define V360_LB_MAIL_IEWR 0xd4
109 #define V360_LB_MAIL_IERd 0xd6
110 #define V360_MAIL_WR_STAT 0xd8
111 #define V360_MAIL_RD_STAT 0xda
113 #define V360_QBA_MAP 0xdc
115 #define V360_DMA_DELAY 0xe0