sys/arch/evbarm/hdl_g/hdlgreg.h

   1 /*      $NetBSD: hdlgreg.h,v 1.1 2006/04/16 02:22:33 nonaka Exp $       */
   2
   3 /*
   4  * Copyright (c) 2005, 2006 Kimihiro Nonaka
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #ifndef _HDLGREG_H_
  30 #define _HDLGREG_H_
  31
  32 /*
  33  * Memory map and register definitions for I-O DATA HDL-G
  34  */
  35
  36 /*
  37  * The memory map of I/O-DATA HDL-G looks like so:
  38  *
  39  *           ------------------------------
  40  *              Intel 80321 IOP Reserved
  41  * FFFF E900 ------------------------------
  42  *              Peripheral Memory Mapped
  43  *                  Registers
  44  * FFFF E000 ------------------------------
  45  *              On-board devices
  46  * FE80 0000 ------------------------------
  47  *              SDRAM
  48  * A000 0000 ------------------------------
  49  *              Reserved
  50  * 9100 0000 ------------------------------
  51  *              Flash
  52  * 9080 0000 ------------------------------
  53  *              Reserved
  54  * 9002 0000 ------------------------------
  55  *              ATU Outbound Transaction
  56  *                  Windows
  57  * 8000 0000 ------------------------------
  58  *              ATU Outbound Direct
  59  *                  Addressing Windows
  60  * 0000 1000 ------------------------------
  61  *              Initialization Boot Code
  62  *                  from Flash
  63  * 0000 0000 ------------------------------
  64  */
  65
  66 /*
  67  * We allocate a page table for VA 0xfe400000 (4MB) and map the
  68  * PCI I/O space (64K) and i80321 memory-mapped registers (4K) there.
  69  */
  70 #define HDLG_IOPXS_VBASE        0xfe400000UL
  71 #define HDLG_IOW_VBASE          HDLG_IOPXS_VBASE
  72 #define HDLG_80321_VBASE        (HDLG_IOW_VBASE + \
  73                                  VERDE_OUT_XLATE_IO_WIN_SIZE)
  74
  75 /*
  76  * The GIGALANDISK on-board devices are mapped VA==PA during bootstrap.
  77  * Conveniently, the size of the on-board register space is 1 section
  78  * mapping.
  79  */
  80 #define HDLG_OBIO_BASE  0xfe800000UL
  81 #define HDLG_OBIO_SIZE  0x00100000UL    /* 1MB */
  82
  83 #define HDLG_UART1      0xfe800000UL    /* TI 16550 */
  84 #define HDLG_PLD        0xfe8d0000UL    /* CPLD */
  85
  86 /*
  87  * CPLD
  88  */
  89 #define HDLG_LEDCTRL            (HDLG_PLD + 0x00)
  90 #define         LEDCTRL_STAT_GREEN      0x01
  91 #define         LEDCTRL_STAT_RED        0x02
  92 #define         LEDCTRL_USB1            0x04
  93 #define         LEDCTRL_USB2            0x08
  94 #define         LEDCTRL_USB3            0x10
  95 #define         LEDCTRL_USB4            0x20
  96 #define         LEDCTRL_HDD             0x40
  97 #define         LEDCTRL_BUZZER          0x80
  98 #define HDLG_PWRLEDCTRL         (HDLG_PLD + 0x01)
  99 #define         PWRLEDCTRL_0            0x01
 100 #define         PWRLEDCTRL_1            0x02
 101 #define         PWRLEDCTRL_2            0x04
 102 #define         PWRLEDCTRL_3            0x08
 103 #define HDLG_BTNSTAT            (HDLG_PLD + 0x02)
 104 #define         BTNSTAT_POWER           0x01
 105 #define         BTNSTAT_SELECT          0x02
 106 #define         BTNSTAT_COPY            0x04
 107 #define         BTNSTAT_REMOVE          0x08
 108 #define         BTNSTAT_RESET           0x10
 109 #define HDLG_INTEN              (HDLG_PLD + 0x03)
 110 #define         INTEN_PWRSW             0x01
 111 #define         INTEN_BUTTON            0x02
 112 #define         INTEN_RTC               0x40
 113 #define HDLG_PWRMNG             (HDLG_PLD + 0x04)
 114 #define         PWRMNG_POWOFF           0x01
 115 #define         PWRMNG_RESET            0x02
 116 #define HDLG_FANCTRL            (HDLG_PLD + 0x06)
 117 #define         FANCTRL_OFF             0x00
 118 #define         FANCTRL_ON              0x01
 119
 120 #define hdlg_enable_pldintr(bit) \
 121 do { \
 122         *(volatile uint8_t *)HDLG_INTEN |= (bit); \
 123 } while (/*CONSTCOND*/0)
 124
 125 #define hdlg_disable_pldintr(bit) \
 126 do { \
 127         *(volatile uint8_t *)HDLG_INTEN &= ~(bit); \
 128 } while (/*CONSTCOND*/0)
 129
 130 #endif /* _HDLGREG_H_ */