sys/arch/evbarm/iq80310/iq80310_pci.c

   1 /*      $NetBSD: iq80310_pci.c,v 1.7.16.3 2004/09/21 13:14:48 skrll Exp $       */
   2
   3 /*
   4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * IQ80310 PCI interrupt support, using he i80312 Companion I/O chip.
  40  */
  41
  42 #include <sys/cdefs.h>
  43 __KERNEL_RCSID(0, "$NetBSD: iq80310_pci.c,v 1.7.16.3 2004/09/21 13:14:48 skrll Exp $");
  44
  45 #include <sys/param.h>
  46 #include <sys/systm.h>
  47 #include <sys/device.h>
  48
  49 #include <machine/autoconf.h>
  50 #include <machine/bus.h>
  51
  52 #include <evbarm/iq80310/iq80310reg.h>
  53 #include <evbarm/iq80310/iq80310var.h>
  54
  55 #include <arm/xscale/i80312reg.h>
  56 #include <arm/xscale/i80312var.h>
  57
  58 #include <dev/pci/pcidevs.h>
  59 #include <dev/pci/ppbreg.h>
  60
  61 int     iq80310_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
  62 const char *iq80310_pci_intr_string(void *, pci_intr_handle_t);
  63 const struct evcnt *iq80310_pci_intr_evcnt(void *, pci_intr_handle_t);
  64 void    *iq80310_pci_intr_establish(void *, pci_intr_handle_t,
  65             int, int (*func)(void *), void *);
  66 void    iq80310_pci_intr_disestablish(void *, void *);
  67
  68 void
  69 iq80310_pci_init(pci_chipset_tag_t pc, void *cookie)
  70 {
  71
  72         pc->pc_intr_v = cookie;         /* the i80312 softc */
  73         pc->pc_intr_map = iq80310_pci_intr_map;
  74         pc->pc_intr_string = iq80310_pci_intr_string;
  75         pc->pc_intr_evcnt = iq80310_pci_intr_evcnt;
  76         pc->pc_intr_establish = iq80310_pci_intr_establish;
  77         pc->pc_intr_disestablish = iq80310_pci_intr_disestablish;
  78 }
  79
  80 #if defined(IOP310_TEAMASA_NPWR)
  81 int
  82 iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
  83 {
  84         struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
  85         pcireg_t reg;
  86         int sbus;
  87
  88         /*
  89          * The Npwr routes #INTA of the on-board PCI devices directly
  90          * through the CPLD.  There is no PCI-PCI bridge and no PCI
  91          * slots on the Npwr.
  92          *
  93          * We also expect the devices to be on the Secondary side of
  94          * the i80312.
  95          */
  96
  97         reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
  98         sbus = PPB_BUSINFO_SECONDARY(reg);
  99
 100         if (pa->pa_bus != sbus) {
 101                 printf("iq80310_pci_intr_map: %d/%d/%d not on Secondary bus\n",
 102                     pa->pa_bus, pa->pa_device, pa->pa_function);
 103                 return (1);
 104         }
 105
 106         switch (pa->pa_device) {
 107         case 5:         /* LSI 53c1010 SCSI */
 108                 *ihp = XINT3_IRQ(2);
 109                 break;
 110         case 6:         /* Intel i82544GC Gig-E #1 */
 111                 *ihp = XINT3_IRQ(1);
 112                 break;
 113         case 7:         /* Intel i82544GC Gig-E #2 */
 114                 *ihp = XINT3_IRQ(4);
 115                 break;
 116         default:
 117                 printf("iq80310_pci_intr_map: no mapping for %d/%d/%d\n",
 118                     pa->pa_bus, pa->pa_device, pa->pa_function);
 119                 return (1);
 120         }
 121
 122         return (0);
 123 }
 124 #else /* Default to stock IQ80310 */
 125 int
 126 iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 127 {
 128         struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
 129         pcitag_t tag;
 130         pcireg_t reg;
 131         int sbus, pbus;
 132
 133         /*
 134          * Mapping of PCI interrupts on the IQ80310 is pretty easy; there
 135          * is a single interrupt line for all PCI devices on pre-F boards,
 136          * and an interrupt line for each INTx# signal on F and later boards.
 137          *
 138          * The only exception is the on-board Ethernet; this devices has
 139          * its own dedicated interrupt line.  The location of this device
 140          * looks like this:
 141          *
 142          *      80312 Secondary -> PPB at dev #7 -> i82559 at dev #0
 143          *
 144          * In order to determine if we're mapping the interrupt for the
 145          * on-board Ethernet, we must read the Secondary Bus # of the
 146          * i80312, then use that to read the Secondary Bus # of the
 147          * 21154 PPB.  At that point, we know that b/d/f of the i82559,
 148          * and can determine if we're looking at that device.
 149          */
 150
 151         reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
 152         pbus = PPB_BUSINFO_PRIMARY(reg);
 153         sbus = PPB_BUSINFO_SECONDARY(reg);
 154
 155         /*
 156          * XXX We don't know how to map interrupts on the Primary
 157          * XXX PCI bus right now.
 158          */
 159         if (pa->pa_bus == pbus) {
 160                 printf("iq80310_pci_intr_map: can't map interrupts on "
 161                     "Primary bus\n");
 162                 return (1);
 163         }
 164
 165         tag = pci_make_tag(pa->pa_pc, sbus, 7, 0);
 166
 167         /* Make sure the PPB is there. */
 168         reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
 169         if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
 170             PCI_VENDOR(reg) == 0) {
 171                 /*
 172                  * That's odd... no PPB there?  Oh well, issue a warning
 173                  * and continue on.
 174                  */
 175                 printf("iq80310_pci_intr_map: PPB not found at %d/%d/%d ??\n",
 176                     sbus, 7, 0);
 177                 goto pinmap;
 178         }
 179
 180         /* Make sure the device that's there is a PPB. */
 181         reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
 182         if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
 183             PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) {
 184                 /*
 185                  * That's odd... the device that's there isn't a PPB.
 186                  * Oh well, issue a warning and continue on.
 187                  */
 188                 printf("iq80310_pci_intr_map: %d/%d/%d isn't a PPB ??\n",
 189                     sbus, 7, 0);
 190                 goto pinmap;
 191         }
 192
 193         /* Now read the PPB's secondary bus number. */
 194         reg = pci_conf_read(pa->pa_pc, tag, PPB_REG_BUSINFO);
 195         sbus = PPB_BUSINFO_SECONDARY(reg);
 196
 197         if (pa->pa_bus == sbus && pa->pa_device == 0 &&
 198             pa->pa_function == 0) {
 199                 /* On-board i82559 Ethernet! */
 200                 *ihp = XINT3_IRQ(XINT3_ETHERNET);
 201                 return (0);
 202         }
 203
 204  pinmap:
 205         if (pa->pa_intrpin == 0) {
 206                 /* No IRQ used. */
 207                 return (1);
 208         }
 209         if (pa->pa_intrpin > 4) {
 210                 printf("iq80310_pci_intr_map: bad interrupt pin %d\n",
 211                     pa->pa_intrpin);
 212                 return (1);
 213         }
 214
 215         /* INTD# is always in XINT3. */
 216         if (pa->pa_intrpin == 4) {
 217                 *ihp = XINT3_IRQ(XINT3_SINTD);
 218                 return (0);
 219         }
 220
 221         /* On pre-F boards, ALL of them are on XINT3. */
 222         if (/*pre-F*/0)
 223                 *ihp = XINT3_IRQ(XINT3_SINTD);
 224         else
 225                 *ihp = XINT0_IRQ(pa->pa_intrpin - 1);
 226
 227         return (0);
 228 }
 229 #endif /* list of IQ80310-based designs */
 230
 231 const char *
 232 iq80310_pci_intr_string(void *v, pci_intr_handle_t ih)
 233 {
 234         static char irqstr[IRQNAMESIZE];
 235
 236         sprintf(irqstr, "iq80310 irq %ld", ih);
 237         return (irqstr);
 238 }
 239
 240 const struct evcnt *
 241 iq80310_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
 242 {
 243
 244         /* XXX For now. */
 245         return (NULL);
 246 }
 247
 248 void *
 249 iq80310_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
 250     int (*func)(void *), void *arg)
 251 {
 252
 253         return (iq80310_intr_establish(ih, ipl, func, arg));
 254 }
 255
 256 void
 257 iq80310_pci_intr_disestablish(void *v, void *cookie)
 258 {
 259
 260         iq80310_intr_disestablish(cookie);
 261 }