sys/arch/evbarm/iq80321/iq80321reg.h

   1 /*      $NetBSD: iq80321reg.h,v 1.4.68.1 2007/06/26 18:12:21 garbled Exp $      */
   2
   3 /*
   4  * Copyright (c) 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _IQ80321REG_H_
  39 #define _IQ80321REG_H_
  40
  41 /*
  42  * Memory map and register definitions for the Intel IQ80321
  43  * Evaluation Board.
  44  */
  45
  46 /*
  47  * The memory map of the IQ80321 looks like so:
  48  *
  49  *           ------------------------------
  50  *              Intel 80321 IOP Reserved
  51  * FFFF E900 ------------------------------
  52  *              Peripheral Memory Mapped
  53  *                  Registers
  54  * FFFF E000 ------------------------------
  55  *              On-board devices
  56  * FE80 0000 ------------------------------
  57  *              SDRAM
  58  * A000 0000 ------------------------------
  59  *              Reserved
  60  * 9100 0000 ------------------------------
  61  *              Flash
  62  * 9080 0000 ------------------------------
  63  *              Reserved
  64  * 9002 0000 ------------------------------
  65  *              ATU Outbound Transaction
  66  *                  Windows
  67  * 8000 0000 ------------------------------
  68  *              ATU Outbound Direct
  69  *                  Addressing Windows
  70  * 0000 1000 ------------------------------
  71  *              Initialization Boot Code
  72  *                  from Flash
  73  * 0000 0000 ------------------------------
  74  */
  75
  76 /*
  77  * We allocate a page table for VA 0xfe400000 (4MB) and map the
  78  * PCI I/O space (64K) and i80321 memory-mapped registers (8K) there.
  79  */
  80 #define IQ80321_IOPXS_VBASE     0xfe400000UL
  81 #define IQ80321_IOW_VBASE       IQ80321_IOPXS_VBASE
  82 #define IQ80321_80321_VBASE     (IQ80321_IOW_VBASE +                    \
  83                                  VERDE_OUT_XLATE_IO_WIN_SIZE)
  84
  85 /*
  86  * The IQ80321 on-board devices are mapped VA==PA during bootstrap.
  87  * Conveniently, the size of the on-board register space is 1 section
  88  * mapping.
  89  */
  90 #define IQ80321_OBIO_BASE       0xfe800000UL
  91 #define IQ80321_OBIO_SIZE       0x00100000UL    /* 1MB */
  92
  93 #define IQ80321_UART1           0xfe800000UL    /* TI 16550 */
  94
  95 #define IQ80321_7SEG_MSB        0xfe840000UL
  96 #define IQ80321_7SEG_LSB        0xfe850000UL
  97
  98 #define IQ80321_ROT_SWITCH      0xfe8d0000UL
  99
 100 #define IQ80321_BATTERY_STAT    0xfe8f0000UL
 101 #define BATTERY_STAT_PRES       (1U << 0)
 102 #define BATTERY_STAT_CHRG       (1U << 1)
 103 #define BATTERY_STAT_DISCHRG    (1U << 2)
 104
 105 #endif /* _IQ80321REG_H_ */