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[netbsd-mini2440.git] / sys / arch / evbarm / lubbock / sacc_obio.c
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1 /* $NetBSD: sacc_obio.c,v 1.9 2009/03/14 15:36:05 dsl Exp $ */
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by IWAMOTO Toshihiro.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * for SA-1111 companion chip on Intel DBPXA250 evaluation board.
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: sacc_obio.c,v 1.9 2009/03/14 15:36:05 dsl Exp $");
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/mbuf.h>
42 #include <sys/socket.h>
43 #include <sys/ioctl.h>
44 #include <sys/errno.h>
45 #include <sys/syslog.h>
46 #include <sys/select.h>
47 #include <sys/device.h>
49 #include <net/if.h>
50 #include <net/if_dl.h>
51 #include <net/if_ether.h>
52 #include <net/if_media.h>
54 #include <machine/intr.h>
55 #include <machine/bus.h>
57 #include <arm/sa11x0/sa1111_reg.h>
58 #include <arm/sa11x0/sa1111_var.h>
59 #include <arm/xscale/pxa2x0cpu.h>
60 #include <arm/xscale/pxa2x0reg.h>
61 #include <arm/xscale/pxa2x0var.h>
62 #include <arm/xscale/pxa2x0_gpio.h>
64 #include <evbarm/lubbock/lubbock_reg.h>
65 #include <evbarm/lubbock/lubbock_var.h>
68 static void sacc_obio_attach(device_t, device_t, void *);
69 static int sacc_obio_intr(void *arg);
71 CFATTACH_DECL_NEW(sacc_obio, sizeof(struct sacc_softc), sacc_probe,
72 sacc_obio_attach, NULL, NULL);
74 #if 0
75 #define DPRINTF(arg) aprint_normal arg
76 #else
77 #define DPRINTF(arg)
78 #endif
80 uint16_t cs2_memctl_init = 0x7ff0;
82 static void
83 sacc_obio_attach(device_t parent, device_t self, void *aux)
85 int i;
86 u_int32_t skid, tmp;
87 struct sacc_softc *sc = device_private(self);
88 struct obio_softc *psc = device_private(parent);
89 struct obio_attach_args *sa = aux;
90 bus_space_tag_t iot = sa->oba_iot;
91 bus_space_handle_t memctl_ioh;
93 aprint_normal("\n");
95 /* Set alternative function for GPIO pings 48..57 on PXA2X0 */
96 for (i=48; i <= 55; ++i)
97 pxa2x0_gpio_set_function(i, GPIO_ALT_FN_2_OUT);
98 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN);
99 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN);
101 /* XXX */
102 if (bus_space_map(iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0,
103 &memctl_ioh))
104 goto fail;
106 tmp = bus_space_read_4(iot, memctl_ioh, MEMCTL_MSC2 );
107 bus_space_write_4(iot, memctl_ioh, MEMCTL_MSC2,
108 (tmp & 0xffff0000) | cs2_memctl_init );
110 bus_space_unmap(iot, memctl_ioh, PXA2X0_MEMCTL_SIZE);
112 sc->sc_dev = self;
113 sc->sc_piot = sc->sc_iot = iot;
114 sc->sc_gpioh = 0; /* not used */
116 if (bus_space_map(iot, sa->oba_addr, 0x2000/*size*/, 0, &sc->sc_ioh))
117 goto fail;
119 skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID);
121 aprint_normal_dev(self, "SA1111 rev %d.%d\n",
122 (skid & 0xf0) >> 4, skid & 0xf);
124 tmp = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR);
125 tmp = (tmp & ~SKCR_VCOOFF) | SKCR_PLLBYPASS;
126 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR, tmp );
128 delay(100); /* XXX */
130 tmp |= SKCR_RCLKEN;
131 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR, tmp );
133 #if 1
134 if( tmp != bus_space_read_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR ) )
135 printf( "!!! FAIL SKCR\n" );
136 #endif
138 /* PCMCIA socket0 power control */
139 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCGPIOA_DVR, 0 );
140 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCGPIOA_DDR, 0 );
142 for(i = 0; i < SACCIC_LEN; i++)
143 sc->sc_intrhand[i] = NULL;
145 /* initialize SA1111 interrupt controller */
146 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0);
147 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0);
148 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0);
149 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
150 SACCIC_INTSTATCLR0, 0xffffffff);
151 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
152 SACCIC_INTSTATCLR1, 0xffffffff);
154 /* connect to On-board peripheral interrupt */
155 obio_intr_establish(psc, sa->oba_intr,
156 IPL_HIGH, sacc_obio_intr, sc );
158 * Attach each devices
160 config_search_ia(sa1111_search, self, "sacc", NULL);
162 return;
164 fail:
165 aprint_normal_dev(self, "unable to map registers\n");
168 static int
169 sacc_obio_intr(void *arg)
171 int i;
172 struct sacc_intrvec intstat;
173 struct sacc_softc *sc = arg;
174 struct sacc_intrhand *ih;
176 intstat.lo =
177 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0);
178 intstat.hi =
179 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1);
180 DPRINTF(("sacc_obio_intr_dispatch: %x %x\n", intstat.lo, intstat.hi));
182 while ((i = find_first_bit(intstat.lo)) >= 0) {
185 * Clear intr status before calling intr handlers.
186 * This cause stray interrupts, but clearing
187 * after calling intr handlers cause intr lossage.
189 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
190 SACCIC_INTSTATCLR0, 1U<<i );
192 for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next)
193 softint_schedule(ih->ih_soft);
195 intstat.lo &= ~(1U<<i);
198 while ((i = find_first_bit(intstat.hi)) >= 0) {
199 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
200 SACCIC_INTSTATCLR1, 1U<<i);
202 for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next)
203 softint_schedule(ih->ih_soft);
205 intstat.hi &= ~(1U<<i);
208 return 1;