sys/arch/evbppc/pmppc/dev/if_cs_mainbus.c

   1 /*      $NetBSD: if_cs_mainbus.c,v 1.3 2008/04/28 20:23:17 martin Exp $ */
   2
   3 /*
   4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __KERNEL_RCSID(0, "$NetBSD: if_cs_mainbus.c,v 1.3 2008/04/28 20:23:17 martin Exp $");
  34
  35 #include <sys/param.h>
  36 #include <sys/device.h>
  37 #include <sys/systm.h>
  38 #include <sys/socket.h>
  39
  40 #include "rnd.h"
  41 #if NRND > 0
  42 #include <sys/rnd.h>
  43 #endif
  44
  45 #include <net/if.h>
  46 #include <net/if_ether.h>
  47 #include <net/if_media.h>
  48 #ifdef INET
  49 #include <netinet/in.h>
  50 #include <netinet/if_inarp.h>
  51 #endif
  52
  53 #include <machine/bus.h>
  54 #include <machine/pio.h>
  55 #include <machine/pmppc.h>
  56 #include <arch/evbppc/pmppc/dev/mainbus.h>
  57
  58 #include <dev/ic/cs89x0reg.h>
  59 #include <dev/ic/cs89x0var.h>
  60
  61 #include <sys/callout.h>
  62
  63 #define ATSN_EEPROM_MAC_OFFSET           0x20
  64
  65
  66 static void     cs_check_eeprom(struct cs_softc *sc);
  67
  68 static int      cs_mainbus_match(struct device *, struct cfdata *, void *);
  69 static void     cs_mainbus_attach(struct device *, struct device *, void *);
  70
  71 CFATTACH_DECL_NEW(cs_mainbus, sizeof(struct cs_softc),
  72     cs_mainbus_match, cs_mainbus_attach, NULL, NULL);
  73
  74 int
  75 cs_mainbus_match(device_t parent, cfdata_t cf, void *aux)
  76 {
  77         struct mainbus_attach_args *maa = aux;
  78
  79         return (strcmp(maa->mb_name, "cs") == 0);
  80 }
  81
  82 #if 0
  83 static u_int64_t
  84 in64(uint a)
  85 {
  86         union {
  87                 double d;
  88                 u_int64_t i;
  89         } u;
  90         double save, *dp = (double *)a;
  91         u_int32_t msr, nmsr;
  92
  93         __asm volatile("mfmsr %0" : "=r"(msr));
  94         nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1);
  95         __asm volatile("mtmsr %0" :: "r"(nmsr));
  96         __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */
  97         __asm volatile(
  98        "stfd 0,%0\n\
  99         lfd 0,%1\n\
 100         stfd 0,%2\n\
 101         lfd 0,%0"
 102                  : "=m"(save), "=m"(*dp)
 103                  : "m"(u.d)
 104                 );
 105         __asm volatile ("eieio; sync");
 106         __asm volatile("mtmsr %0" :: "r"(msr));
 107         return (u.i);
 108 }
 109 #endif
 110
 111 static void
 112 out64(uint a, u_int64_t v)
 113 {
 114         union {
 115                 double d;
 116                 u_int64_t i;
 117         } u;
 118         double save, *dp = (double *)a;
 119         u_int32_t msr, nmsr;
 120         int s;
 121
 122         s = splhigh();
 123         u.i = v;
 124         __asm volatile("mfmsr %0" : "=r"(msr));
 125         nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1);
 126         __asm volatile("mtmsr %0" :: "r"(nmsr));
 127         __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */
 128         __asm volatile(
 129        "stfd 0,%0\n\
 130         lfd 0,%2\n\
 131         stfd 0,%1\n\
 132         lfd 0,%0"
 133                  : "=m"(save), "=m"(*dp)
 134                  : "m"(u.d)
 135                 );
 136         __asm volatile ("eieio; sync");
 137         __asm volatile("mtmsr %0" :: "r"(msr));
 138         splx(s);
 139 }
 140
 141 static u_int8_t
 142 cs_io_read_1(struct cs_softc *sc, bus_size_t offs)
 143 {
 144         u_int32_t a, v;
 145
 146         a = sc->sc_ioh + (offs << 2);
 147         v = in8(a);
 148         return v;
 149 }
 150
 151 static u_int16_t
 152 cs_io_read_2(struct cs_softc *sc, bus_size_t offs)
 153 {
 154         u_int32_t a, v;
 155
 156         a = sc->sc_ioh + (offs << 2);
 157         v = in16(a);
 158         return v;
 159 }
 160
 161 static void
 162 cs_io_read_multi_2(struct cs_softc *sc, bus_size_t offs, u_int16_t *buf,
 163                    bus_size_t cnt)
 164 {
 165         u_int32_t a, v;
 166
 167         a = sc->sc_ioh + (offs << 2);
 168         while (cnt--) {
 169                 v = in16(a);
 170                 *buf++ = bswap16(v);
 171         }
 172 }
 173
 174 static void
 175 cs_io_write_2(struct cs_softc *sc, bus_size_t offs, u_int16_t data)
 176 {
 177         u_int32_t a;
 178         u_int64_t v;
 179
 180         a = sc->sc_ioh + (offs << 2);
 181         v = (u_int64_t)data << 48;
 182         out64(a, v);
 183
 184         (void)in16(a);          /* CPC700 write post bug */
 185 }
 186
 187 static void
 188 cs_io_write_multi_2(struct cs_softc *sc, bus_size_t offs,
 189                     const u_int16_t *buf, bus_size_t cnt)
 190 {
 191         u_int16_t v;
 192         double save, *dp;
 193         union {
 194                 double d;
 195                 u_int64_t i;
 196         } u;
 197         u_int32_t msr, nmsr;
 198         int s;
 199
 200         dp = (double *)(sc->sc_ioh + (offs << 2));
 201
 202         s = splhigh();
 203         __asm volatile("mfmsr %0" : "=r"(msr));
 204         nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1);
 205         __asm volatile("mtmsr %0" :: "r"(nmsr));
 206         __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */
 207         __asm volatile("stfd 0,%0" : "=m"(save));
 208
 209         while (cnt--) {
 210                 v = *buf++;
 211                 v = bswap16(v);
 212                 u.i = (u_int64_t)v << 48;
 213                 __asm volatile("lfd 0,%1\nstfd 0,%0" : "=m"(*dp) : "m"(u.d) );
 214                 __asm volatile ("eieio; sync");
 215         }
 216         __asm volatile("lfd 0,%0" :: "m"(save));
 217         __asm volatile("mtmsr %0" :: "r"(msr));
 218         splx(s);
 219 }
 220
 221 static u_int16_t
 222 cs_mem_read_2(struct cs_softc *sc, bus_size_t offs)
 223 {
 224         panic("cs_mem_read_2");
 225 }
 226
 227 static void
 228 cs_mem_write_2(struct cs_softc *sc, bus_size_t offs, u_int16_t data)
 229 {
 230         panic("cs_mem_write_2");
 231 }
 232
 233 static void
 234 cs_mem_write_region_2(struct cs_softc *sc, bus_size_t offs,
 235                       const u_int16_t *buf, bus_size_t cnt)
 236 {
 237         panic("cs_mem_write_region_2");
 238 }
 239
 240 void
 241 cs_mainbus_attach(device_t parent, device_t self, void *aux)
 242 {
 243         struct cs_softc *sc = device_private(self);
 244         struct mainbus_attach_args *maa = aux;
 245         int media[1] = { IFM_ETHER | IFM_10_T };
 246
 247         printf("\n");
 248
 249         sc->sc_dev = self;
 250         sc->sc_iot = maa->mb_bt;
 251         sc->sc_memt = maa->mb_bt;
 252         sc->sc_irq = maa->mb_irq;
 253
 254         if (bus_space_map(sc->sc_iot, PMPPC_CS_IO, CS8900_IOSIZE*4,
 255                           0, &sc->sc_ioh)) {
 256                 printf("%s: failed to map io\n", device_xname(self));
 257                 return;
 258         }
 259
 260         cs_check_eeprom(sc);
 261
 262         sc->sc_ih = intr_establish(sc->sc_irq, IST_LEVEL, IPL_NET, cs_intr, sc);
 263         if (!sc->sc_ih) {
 264                 printf("%s: unable to establish interrupt\n",
 265                     device_xname(self));
 266                 goto fail;
 267         }
 268
 269         sc->sc_cfgflags = CFGFLG_NOT_EEPROM;
 270
 271         sc->sc_io_read_1 = cs_io_read_1;
 272         sc->sc_io_read_2 = cs_io_read_2;
 273         sc->sc_io_read_multi_2 = cs_io_read_multi_2;
 274         sc->sc_io_write_2 = cs_io_write_2;
 275         sc->sc_io_write_multi_2 = cs_io_write_multi_2;
 276         sc->sc_mem_read_2 = cs_mem_read_2;
 277         sc->sc_mem_write_2 = cs_mem_write_2;
 278         sc->sc_mem_write_region_2 = cs_mem_write_region_2;
 279
 280         /*
 281          * We need interrupt on INTRQ0 from the CS8900 (that's what wired
 282          * to the UIC).  The MI driver subtracts 10 from the irq, so
 283          * use 10 as the irq.
 284          */
 285         sc->sc_irq = 10;
 286
 287         /* Use half duplex 10baseT. */
 288         if (cs_attach(sc, NULL, media, 1, IFM_ETHER | IFM_10_T)) {
 289                 printf("%s: unable to attach\n", device_xname(self));
 290                 goto fail;
 291         }
 292
 293         return;
 294
 295  fail:
 296         /* XXX disestablish, unmap */
 297         return;
 298 }
 299
 300
 301 /*
 302  * EEPROM initialization code.
 303  */
 304
 305 static uint16_t default_eeprom_cfg[] =
 306 { 0xA100, 0x2020, 0x0300, 0x0000, 0x0000,
 307   0x102C, 0x1000, 0x0008, 0x2158, 0x0000,
 308   0x0000, 0x0000 };
 309
 310 static uint16_t
 311 cs_readreg(struct cs_softc *sc, uint pp_offset)
 312 {
 313         cs_io_write_2(sc, PORT_PKTPG_PTR, pp_offset);
 314         (void)cs_io_read_2(sc, PORT_PKTPG_PTR);
 315         return (cs_io_read_2(sc, PORT_PKTPG_DATA));
 316 }
 317
 318 static void
 319 cs_writereg(struct cs_softc *sc, uint pp_offset, uint16_t value)
 320 {
 321         cs_io_write_2(sc, PORT_PKTPG_PTR, pp_offset);
 322         (void)cs_io_read_2(sc, PORT_PKTPG_PTR);
 323         cs_io_write_2(sc, PORT_PKTPG_DATA, value);
 324         (void)cs_io_read_2(sc, PORT_PKTPG_DATA);
 325 }
 326
 327 static int
 328 cs_wait_eeprom_ready(struct cs_softc *sc)
 329 {
 330         int ms;
 331
 332         /*
 333          * Check to see if the EEPROM is ready, a timeout is used -
 334          * just in case EEPROM is ready when SI_BUSY in the
 335          * PP_SelfST is clear.
 336          */
 337         ms = 0;
 338         while(cs_readreg(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY) {
 339                 delay(1000);
 340                 if (ms++ > 20)
 341                         return 0;
 342         }
 343         return 1;
 344 }
 345
 346 static void
 347 cs_wr_eeprom(struct cs_softc *sc, uint16_t offset, uint16_t data)
 348 {
 349
 350         /* Check to make sure EEPROM is ready. */
 351         if (!cs_wait_eeprom_ready(sc)) {
 352                 printf("%s: write EEPROM not ready\n",
 353                     device_xname(sc->sc_dev));
 354                 return;
 355         }
 356
 357         /* Enable writing. */
 358         cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_WRITE_ENABLE);
 359
 360         /* Wait for WRITE_ENABLE command to complete. */
 361         if (!cs_wait_eeprom_ready(sc)) {
 362                 printf("%s: EEPROM WRITE_ENABLE timeout",
 363                     device_xname(sc->sc_dev));
 364         } else {
 365                 /* Write data into EEPROM_DATA register. */
 366                 cs_writereg(sc, PKTPG_EEPROM_DATA, data);
 367                 delay(1000);
 368                 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_CMD_WRITE | offset);
 369
 370                 /* Wait for WRITE_REGISTER command to complete. */
 371                 if (!cs_wait_eeprom_ready(sc)) {
 372                         printf("%s: EEPROM WRITE_REGISTER timeout\n",
 373                             device_xname(sc->sc_dev));
 374                 }
 375         }
 376
 377         /* Disable writing. */
 378         cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_WRITE_DISABLE);
 379
 380         /* Wait for WRITE_DISABLE command to complete. */
 381         if (!cs_wait_eeprom_ready(sc)) {
 382                 printf("%s: WRITE_DISABLE timeout\n", device_xname(sc->sc_dev));
 383         }
 384 }
 385
 386 static uint16_t
 387 cs_rd_eeprom(struct cs_softc *sc, uint16_t offset)
 388 {
 389
 390         if (!cs_wait_eeprom_ready(sc)) {
 391                 printf("%s: read EEPROM not ready\n", device_xname(sc->sc_dev));
 392                 return 0;
 393         }
 394         cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_CMD_READ | offset);
 395
 396         if (!cs_wait_eeprom_ready(sc)) {
 397                 printf("%s: EEPROM_READ timeout\n", device_xname(sc->sc_dev));
 398                 return 0;
 399         }
 400         return cs_readreg(sc, PKTPG_EEPROM_DATA);
 401 }
 402
 403 static void
 404 cs_check_eeprom(struct cs_softc *sc)
 405 {
 406         uint8_t checksum;
 407         int i;
 408         uint16_t tmp;
 409
 410         /*
 411          * If the SELFST[EEPROMOK] is set, then assume EEPROM configuration
 412          * is valid.
 413          */
 414         if (cs_readreg(sc, PKTPG_SELF_ST) & SELF_ST_EEP_OK) {
 415                 printf("%s: EEPROM OK, skipping initialization\n",
 416                     device_xname(sc->sc_dev));
 417                 return;
 418         }
 419         printf("%s: updating EEPROM\n", device_xname(sc->sc_dev));
 420
 421         /*
 422          * Calculate the size (in bytes) of the default config array and write
 423          * it to the lower byte of the array itself.
 424          */
 425         default_eeprom_cfg[0] |= sizeof(default_eeprom_cfg);
 426
 427         /*
 428          * Read the MAC address from its Artesyn-specified offset in the EEPROM.
 429          */
 430         for (i = 0; i < 3; i++) {
 431                 tmp = cs_rd_eeprom(sc, ATSN_EEPROM_MAC_OFFSET + i);
 432                 default_eeprom_cfg[EEPROM_MAC + i] = bswap16(tmp);
 433         }
 434
 435         /*
 436          * Program the EEPROM with our default configuration,
 437          * calculating checksum as we proceed.
 438          */
 439         checksum = 0;
 440         for (i = 0; i < sizeof(default_eeprom_cfg)/2 ; i++) {
 441                 tmp = default_eeprom_cfg[i];
 442                 cs_wr_eeprom(sc, i, tmp);
 443                 checksum += tmp >> 8;
 444                 checksum += tmp & 0xff;
 445         }
 446
 447         /*
 448          * The CS8900a datasheet calls for the two's complement of the checksum
 449          * to be prgrammed in the most significant byte of the last word of the
 450          * header.
 451          */
 452         checksum = ~checksum + 1;
 453         cs_wr_eeprom(sc, i++, checksum << 8);
 454         /* write "end of data" flag */
 455         cs_wr_eeprom(sc, i, 0xffff);
 456 }