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[netbsd-mini2440.git] / sys / arch / hp700 / dev / dino.c
blobb24a2fbb60d72ac3070089a912adc7ff2cc0de65
1 /* $NetBSD: dino.c,v 1.20 2009/12/08 07:32:45 skrll Exp $ */
2
3 /* $OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $ */
4
5 /*
6 * Copyright (c) 2003 Michael Shalayeff
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: dino.c,v 1.20 2009/12/08 07:32:45 skrll Exp $");
33
34 /* #include "cardbus.h" */
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/device.h>
39 #include <sys/reboot.h>
40 #include <sys/malloc.h>
41 #include <sys/extent.h>
42
43 #include <machine/iomod.h>
44 #include <machine/autoconf.h>
45 #include <machine/intr.h>
46 #include <hp700/hp700/intr.h>
47
48 #include <hppa/include/vmparam.h>
49 #include <hp700/dev/cpudevs.h>
50
51 #if NCARDBUS > 0
52 #include <dev/cardbus/rbus.h>
53 #endif
54
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pcidevs.h>
58
59 #define DINO_MEM_CHUNK 0x800000
60
61 /* from machdep.c */
62 extern struct extent *hp700_io_extent;
63
64 struct dino_regs {
65 uint32_t pad0; /* 0x000 */
66 uint32_t iar0; /* 0x004 rw intr addr reg 0 */
67 uint32_t iodc; /* 0x008 rw iodc data/addr */
68 uint32_t irr0; /* 0x00c r intr req reg 0 */
69 uint32_t iar1; /* 0x010 rw intr addr reg 1 */
70 uint32_t irr1; /* 0x014 r intr req reg 1 */
71 uint32_t imr; /* 0x018 rw intr mask reg */
72 uint32_t ipr; /* 0x01c rw intr pending reg */
73 uint32_t toc_addr; /* 0x020 rw TOC addr reg */
74 uint32_t icr; /* 0x024 rw intr control reg */
75 uint32_t ilr; /* 0x028 r intr level reg */
76 uint32_t pad1; /* 0x02c */
77 uint32_t io_command; /* 0x030 w command register */
78 uint32_t io_status; /* 0x034 r status register */
79 uint32_t io_control; /* 0x038 rw control register */
80 uint32_t pad2; /* 0x03c AUX registers follow */
81 uint32_t io_gsc_err_addr;/* 0x040 GSC error address */
82 uint32_t io_err_info; /* 0x044 error info register */
83 uint32_t io_pci_err_addr;/* 0x048 PCI error address */
84 uint32_t pad3[4]; /* 0x04c */
85 uint32_t io_fbb_en; /* 0x05c fast back2back enable reg */
86 uint32_t io_addr_en; /* 0x060 address enable reg */
87 uint32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */
88 uint32_t pci_conf_data; /* 0x068 PCI conf data reg */
89 uint32_t pci_io_data; /* 0x06c PCI io data reg */
90 uint32_t pci_mem_data; /* 0x070 PCI memory data reg */
91 uint32_t pad4[0x740/4]; /* 0x074 */
92 uint32_t gsc2x_config; /* 0x7b4 GSC2X config reg */
93 uint32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */
94 uint32_t gmask; /* 0x800 GSC arbitration mask */
95 uint32_t pamr; /* 0x804 PCI arbitration mask */
96 uint32_t papr; /* 0x808 PCI arbitration priority */
97 uint32_t damode; /* 0x80c PCI arbitration mode */
98 uint32_t pcicmd; /* 0x810 PCI command register */
99 uint32_t pcists; /* 0x814 PCI status register */
100 uint32_t pad6; /* 0x818 */
101 uint32_t mltim; /* 0x81c PCI master latency timer */
102 uint32_t brdg_feat; /* 0x820 PCI bridge feature enable */
103 uint32_t pciror; /* 0x824 PCI read optimization reg */
104 uint32_t pciwor; /* 0x828 PCI write optimization reg */
105 uint32_t pad7; /* 0x82c */
106 uint32_t tltim; /* 0x830 PCI target latency reg */
107 };
108
109 struct dino_softc {
110 device_t sc_dv;
111
112 int sc_ver;
113 void *sc_ih;
114 struct hp700_int_reg sc_int_reg;
115 bus_space_tag_t sc_bt;
116 bus_space_handle_t sc_bh;
117 bus_dma_tag_t sc_dmat;
118 volatile struct dino_regs *sc_regs;
119
120 struct hppa_pci_chipset_tag sc_pc;
121 struct hppa_bus_space_tag sc_iot;
122 char sc_ioexname[20];
123 struct extent *sc_ioex;
124 struct hppa_bus_space_tag sc_memt;
125 int sc_memrefcount[30];
126 struct hppa_bus_dma_tag sc_dmatag;
127 };
128
129 int dinomatch(device_t, struct cfdata *, void *);
130 void dinoattach(device_t, device_t, void *);
131 static void dino_callback(device_t, struct confargs *);
132
133 CFATTACH_DECL_NEW(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL,
134 NULL);
135
136
137 void dino_attach_hook(device_t, device_t,
138 struct pcibus_attach_args *);
139 void dino_enable_bus(struct dino_softc *, int);
140 int dino_maxdevs(void *, int);
141 pcitag_t dino_make_tag(void *, int, int, int);
142 void dino_decompose_tag(void *, pcitag_t, int *, int *, int *);
143 pcireg_t dino_conf_read(void *, pcitag_t, int);
144 void dino_conf_write(void *, pcitag_t, int, pcireg_t);
145
146 int dino_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
147 const char *dino_intr_string(void *, pci_intr_handle_t);
148 void *dino_intr_establish(void *, pci_intr_handle_t, int,
149 int (*)(void *), void *);
150 void dino_intr_disestablish(void *, void *);
151
152 void *dino_alloc_parent(device_t, struct pci_attach_args *, int);
153
154 int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *);
155 int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *);
156 int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t,
157 bus_space_handle_t *);
158 int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t,
159 bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *);
160 int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t,
161 bus_size_t, int, bus_addr_t *, bus_space_handle_t *);
162 void dino_unmap(void *, bus_space_handle_t, bus_size_t);
163 void dino_free(void *, bus_space_handle_t, bus_size_t);
164 void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int);
165 void *dino_vaddr(void *, bus_space_handle_t);
166 paddr_t dino_mmap(void *, bus_addr_t, off_t, int, int);
167
168 uint8_t dino_r1(void *, bus_space_handle_t, bus_size_t);
169 uint16_t dino_r2(void *, bus_space_handle_t, bus_size_t);
170 uint32_t dino_r4(void *, bus_space_handle_t, bus_size_t);
171 uint64_t dino_r8(void *, bus_space_handle_t, bus_size_t);
172 void dino_w1(void *, bus_space_handle_t, bus_size_t, uint8_t);
173 void dino_w2(void *, bus_space_handle_t, bus_size_t, uint16_t);
174 void dino_w4(void *, bus_space_handle_t, bus_size_t, uint32_t);
175 void dino_w8(void *, bus_space_handle_t, bus_size_t, uint64_t);
176 void dino_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t);
177 void dino_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t);
178 void dino_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t);
179 void dino_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t);
180 void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
181 bus_size_t);
182 void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
183 bus_size_t);
184 void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
185 bus_size_t);
186 void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
187 bus_size_t);
188 void dino_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t);
189 void dino_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t);
190 void dino_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t);
191 void dino_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t);
192 void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
193 bus_size_t);
194 void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
195 bus_size_t);
196 void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
197 bus_size_t);
198 void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
199 bus_size_t);
200 void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
201 bus_size_t);
202 void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
203 bus_size_t);
204 void dino_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t);
205 void dino_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t);
206 void dino_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t);
207 void dino_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t);
208 void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
209 bus_size_t);
210 void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
211 bus_size_t);
212 void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
213 bus_size_t);
214 void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
215 bus_size_t);
216 void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
217 bus_size_t);
218 void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
219 bus_size_t);
220 void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
221 bus_size_t);
222 void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
223 bus_size_t);
224 void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
225 bus_size_t);
226 void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
227 bus_size_t);
228 void dino_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t);
229 void dino_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t);
230 void dino_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t);
231 void dino_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t);
232 void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
233 bus_size_t, bus_size_t);
234 void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
235 bus_size_t, bus_size_t);
236 void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
237 bus_size_t, bus_size_t);
238 void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
239 bus_size_t, bus_size_t);
240 int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int,
241 bus_dmamap_t *);
242 void dino_dmamap_destroy(void *, bus_dmamap_t);
243 int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *,
244 int);
245 int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int);
246 int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int);
247 int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int,
248 bus_size_t, int);
249 void dino_dmamap_unload(void *, bus_dmamap_t);
250 void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int);
251 int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t,
252 bus_dma_segment_t *, int, int *, int);
253 void dino_dmamem_free(void *, bus_dma_segment_t *, int);
254 int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, void **, int);
255 void dino_dmamem_unmap(void *, void *, size_t);
256 paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int);
257
258
259 void
260 dino_attach_hook(device_t parent, device_t self,
261 struct pcibus_attach_args *pba)
262 {
263 struct dino_softc *sc = pba->pba_pc->_cookie;
264
265 /*
266 * The firmware enables only devices that are needed for booting.
267 * So other devices will fail to map PCI MEM / IO when they attach.
268 * Therefore we recursively walk all buses to simply enable everything.
269 */
270 dino_enable_bus(sc, 0);
271 }
272
273 void
274 dino_enable_bus(struct dino_softc *sc, int bus)
275 {
276 int func;
277 int dev;
278 pcitag_t tag;
279 pcireg_t data;
280 pcireg_t class;
281
282 for (dev = 0; dev < 32; dev++) {
283 tag = dino_make_tag(sc, bus, dev, 0);
284 if (tag != -1 && dino_conf_read(sc, tag, 0) != 0xffffffff) {
285 for (func = 0; func < 8; func++) {
286 tag = dino_make_tag(sc, bus, dev, func);
287 if (dino_conf_read(sc, tag, 0) != 0xffffffff) {
288 data = dino_conf_read(sc, tag,
289 PCI_COMMAND_STATUS_REG);
290 dino_conf_write(sc, tag,
291 PCI_COMMAND_STATUS_REG,
292 PCI_COMMAND_IO_ENABLE |
293 PCI_COMMAND_MEM_ENABLE |
294 PCI_COMMAND_MASTER_ENABLE | data);
295 }
296 }
297 class = dino_conf_read(sc, tag, PCI_CLASS_REG);
298 if (PCI_CLASS(class) == PCI_CLASS_BRIDGE &&
299 PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)
300 dino_enable_bus(sc, bus + 1);
301 }
302 }
303 }
304
305 int
306 dino_maxdevs(void *v, int bus)
307 {
308 return 32;
309 }
310
311 pcitag_t
312 dino_make_tag(void *v, int bus, int dev, int func)
313 {
314 if (bus > 255 || dev > 31 || func > 7)
315 panic("dino_make_tag: bad request");
316
317 return (bus << 16) | (dev << 11) | (func << 8);
318 }
319
320 void
321 dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func)
322 {
323 *bus = (tag >> 16) & 0xff;
324 *dev = (tag >> 11) & 0x1f;
325 *func= (tag >> 8) & 0x07;
326 }
327
328 pcireg_t
329 dino_conf_read(void *v, pcitag_t tag, int reg)
330 {
331 struct dino_softc *sc = v;
332 volatile struct dino_regs *r = sc->sc_regs;
333 pcireg_t data;
334 uint32_t pamr;
335
336 /* fix arbitration errata by disabling all pci devs on config read */
337 pamr = r->pamr;
338 r->pamr = 0;
339
340 r->pci_addr = tag | reg;
341 data = r->pci_conf_data;
342
343 /* restore arbitration */
344 r->pamr = pamr;
345
346 return le32toh(data);
347 }
348
349 void
350 dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
351 {
352 struct dino_softc *sc = v;
353 volatile struct dino_regs *r = sc->sc_regs;
354 pcireg_t data1;
355 uint32_t pamr;
356
357 /* fix arbitration errata by disabling all pci devs on config read */
358 pamr = r->pamr;
359 r->pamr = 0;
360
361 r->pci_addr = tag | reg;
362 r->pci_conf_data = htole32(data);
363
364 /* fix coalescing config and io writes by interleaving w/ a read */
365 r->pci_addr = tag | PCI_ID_REG;
366 data1 = r->pci_conf_data;
367
368 /* restore arbitration */
369 r->pamr = pamr;
370 }
371
372 int
373 dino_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
374 {
375 int line = pa->pa_intrline;
376
377 if (line == 0xff)
378 return 1;
379
380 *ihp = line;
381
382 return 0;
383 }
384
385 const char *
386 dino_intr_string(void *v, pci_intr_handle_t ih)
387 {
388 static char buf[32];
389
390 snprintf(buf, 32, "irq %ld", ih);
391 return buf;
392 }
393
394 extern int cold;
395
396
397 void *
398 dino_intr_establish(void *v, pci_intr_handle_t ih,
399 int pri, int (*handler)(void *), void *arg)
400 {
401 struct dino_softc *sc = v;
402
403 return hp700_intr_establish(sc->sc_dv, pri, handler, arg,
404 &sc->sc_int_reg, ih);
405 }
406
407 void
408 dino_intr_disestablish(void *v, void *cookie)
409 {
410 /* XXX Implement me */
411 }
412
413
414 #if NCARDBUS > 0
415 void *
416 dino_alloc_parent(device_t self, struct pci_attach_args *pa, int io)
417 {
418 struct dino_softc *sc = pa->pa_pc->_cookie;
419 struct extent *ex;
420 bus_space_tag_t tag;
421 bus_addr_t start;
422 bus_size_t size;
423
424 if (io) {
425 ex = sc->sc_ioex;
426 tag = pa->pa_iot;
427 start = 0xa000;
428 size = 0x1000;
429 } else {
430 ex = hp700_io_extent;
431 tag = pa->pa_memt;
432 start = ex->ex_start; /* XXX or 0xf0800000? */
433 size = DINO_MEM_CHUNK;
434 }
435
436 if (extent_alloc_subregion(ex, start, ex->ex_end, size, size,
437 EX_NOBOUNDARY, EX_NOWAIT, &start))
438 return NULL;
439 extent_free(ex, start, size, EX_NOWAIT);
440 return rbus_new_root_share(tag, ex, start, size, start);
441 }
442 #endif
443
444 int
445 dino_iomap(void *v, bus_addr_t bpa, bus_size_t size,
446 int flags, bus_space_handle_t *bshp)
447 {
448 struct dino_softc *sc = v;
449 int error;
450
451 if (!(flags & BUS_SPACE_MAP_NOEXTENT) &&
452 (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT)))
453 return error;
454
455 if (bshp)
456 *bshp = bpa;
457
458 return 0;
459 }
460
461 int
462 dino_memmap(void *v, bus_addr_t bpa, bus_size_t size,
463 int flags, bus_space_handle_t *bshp)
464 {
465 struct dino_softc *sc = v;
466 volatile struct dino_regs *r = sc->sc_regs;
467 uint32_t reg;
468 int error;
469
470 reg = r->io_addr_en;
471 reg |= 1 << ((bpa >> 23) & 0x1f);
472 #ifdef DEBUG
473 if (reg & 0x80000001)
474 panic("mapping outside the mem extent range");
475 #endif
476 if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp)))
477 return error;
478 ++sc->sc_memrefcount[((bpa >> 23) & 0x1f)];
479 /* map into the upper bus space, if not yet mapped this 8M */
480 if (reg != r->io_addr_en)
481 r->io_addr_en = reg;
482 return 0;
483 }
484
485 int
486 dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset,
487 bus_size_t size, bus_space_handle_t *nbshp)
488 {
489 *nbshp = bsh + offset;
490 return 0;
491 }
492
493 int
494 dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
495 bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp,
496 bus_space_handle_t *bshp)
497 {
498 struct dino_softc *sc = v;
499 struct extent *ex = sc->sc_ioex;
500 bus_addr_t bpa;
501 int error;
502
503 if (rstart < ex->ex_start || rend > ex->ex_end)
504 panic("dino_ioalloc: bad region start/end");
505
506 if ((error = extent_alloc_subregion(ex, rstart, rend, size,
507 align, boundary, EX_NOWAIT, &bpa)))
508 return error;
509
510 if (addrp)
511 *addrp = bpa;
512 if (bshp)
513 *bshp = bpa;
514
515 return 0;
516 }
517
518 int
519 dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
520 bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp,
521 bus_space_handle_t *bshp)
522 {
523 struct dino_softc *sc = v;
524 volatile struct dino_regs *r = sc->sc_regs;
525 uint32_t reg;
526 int i, error;
527
528 /*
529 * Allow allocation only when PCI MEM is already mapped.
530 * Needed to avoid allocation of I/O space used by devices that
531 * have no driver in the current kernel.
532 * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only.
533 */
534 reg = r->io_addr_en;
535 if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0)
536 return -1;
537 /* Find used PCI MEM and narrow allocateble region down to it. */
538 for (i = 1; i < 31; i++)
539 if ((reg & 1 << i) != 0) {
540 rstart = 0xf0000000 | i << 23;
541 rend = (0xf0000000 | (i + 1) << 23) - 1;
542 break;
543 }
544 if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align,
545 boundary, flags, addrp, bshp)))
546 return error;
547 ++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)];
548 return 0;
549 }
550
551 void
552 dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size)
553 {
554 struct dino_softc *sc = v;
555 volatile struct dino_regs *r = sc->sc_regs;
556
557 if (bsh & 0xf0000000) {
558 bus_space_unmap(sc->sc_bt, bsh, size);
559 if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0)
560 /* Unmap the upper PCI MEM space. */
561 r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f));
562 } else {
563 /* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */
564 if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT))
565 printf("dino_unmap: ps 0x%lx, size 0x%lx\n"
566 "dino_unmap: can't free region\n", bsh, size);
567 }
568 }
569
570 void
571 dino_free(void *v, bus_space_handle_t bh, bus_size_t size)
572 {
573 /* should be enough */
574 dino_unmap(v, bh, size);
575 }
576
577 void
578 dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op)
579 {
580 sync_caches();
581 }
582
583 void*
584 dino_vaddr(void *v, bus_space_handle_t h)
585 {
586 struct dino_softc *sc = v;
587
588 return bus_space_vaddr(sc->sc_bt, h);
589 }
590
591 paddr_t
592 dino_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags)
593 {
594 return -1;
595 }
596
597 uint8_t
598 dino_r1(void *v, bus_space_handle_t h, bus_size_t o)
599 {
600 h += o;
601 if (h & 0xf0000000)
602 return *(volatile uint8_t *)h;
603 else {
604 struct dino_softc *sc = v;
605 volatile struct dino_regs *r = sc->sc_regs;
606
607 r->pci_addr = h;
608 return *((volatile uint8_t *)&r->pci_io_data + (h & 3));
609 }
610 }
611
612 uint16_t
613 dino_r2(void *v, bus_space_handle_t h, bus_size_t o)
614 {
615 volatile uint16_t *p;
616
617 h += o;
618 if (h & 0xf0000000)
619 p = (volatile uint16_t *)h;
620 else {
621 struct dino_softc *sc = v;
622 volatile struct dino_regs *r = sc->sc_regs;
623
624 r->pci_addr = h;
625 p = (volatile uint16_t *)&r->pci_io_data;
626 if (h & 2)
627 p++;
628 }
629 return le16toh(*p);
630 }
631
632 uint32_t
633 dino_r4(void *v, bus_space_handle_t h, bus_size_t o)
634 {
635 uint32_t data;
636
637 h += o;
638 if (h & 0xf0000000)
639 data = *(volatile uint32_t *)h;
640 else {
641 struct dino_softc *sc = v;
642 volatile struct dino_regs *r = sc->sc_regs;
643
644 r->pci_addr = h;
645 data = r->pci_io_data;
646 }
647
648 return le32toh(data);
649 }
650
651 uint64_t
652 dino_r8(void *v, bus_space_handle_t h, bus_size_t o)
653 {
654 uint64_t data;
655
656 h += o;
657 if (h & 0xf0000000)
658 data = *(volatile uint64_t *)h;
659 else
660 panic("dino_r8: not implemented");
661
662 return le64toh(data);
663 }
664
665 void
666 dino_w1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv)
667 {
668 h += o;
669 if (h & 0xf0000000)
670 *(volatile uint8_t *)h = vv;
671 else {
672 struct dino_softc *sc = v;
673 volatile struct dino_regs *r = sc->sc_regs;
674
675 r->pci_addr = h;
676 *((volatile uint8_t *)&r->pci_io_data + (h & 3)) = vv;
677 }
678 }
679
680 void
681 dino_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv)
682 {
683 volatile uint16_t *p;
684
685 h += o;
686 if (h & 0xf0000000)
687 p = (volatile uint16_t *)h;
688 else {
689 struct dino_softc *sc = v;
690 volatile struct dino_regs *r = sc->sc_regs;
691
692 r->pci_addr = h;
693 p = (volatile uint16_t *)&r->pci_io_data;
694 if (h & 2)
695 p++;
696 }
697
698 *p = htole16(vv);
699 }
700
701 void
702 dino_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv)
703 {
704 h += o;
705 vv = htole32(vv);
706 if (h & 0xf0000000)
707 *(volatile uint32_t *)h = vv;
708 else {
709 struct dino_softc *sc = v;
710 volatile struct dino_regs *r = sc->sc_regs;
711
712 r->pci_addr = h;
713 r->pci_io_data = vv;
714 }
715 }
716
717 void
718 dino_w8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv)
719 {
720 h += o;
721 if (h & 0xf0000000)
722 *(volatile uint64_t *)h = htole64(vv);
723 else
724 panic("dino_w8: not implemented");
725 }
726
727
728 void
729 dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c)
730 {
731 volatile uint8_t *p;
732
733 h += o;
734 if (h & 0xf0000000)
735 p = (volatile uint8_t *)h;
736 else {
737 struct dino_softc *sc = v;
738 volatile struct dino_regs *r = sc->sc_regs;
739
740 r->pci_addr = h;
741 p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
742 }
743
744 while (c--)
745 *a++ = *p;
746 }
747
748 void
749 dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c)
750 {
751 volatile uint16_t *p;
752
753 h += o;
754 if (h & 0xf0000000)
755 p = (volatile uint16_t *)h;
756 else {
757 struct dino_softc *sc = v;
758 volatile struct dino_regs *r = sc->sc_regs;
759
760 r->pci_addr = h;
761 p = (volatile uint16_t *)&r->pci_io_data;
762 if (h & 2)
763 p++;
764 }
765
766 while (c--)
767 *a++ = le16toh(*p);
768 }
769
770 void
771 dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c)
772 {
773 volatile uint32_t *p;
774
775 h += o;
776 if (h & 0xf0000000)
777 p = (volatile uint32_t *)h;
778 else {
779 struct dino_softc *sc = v;
780 volatile struct dino_regs *r = sc->sc_regs;
781
782 r->pci_addr = h;
783 p = (volatile uint32_t *)&r->pci_io_data;
784 }
785
786 while (c--)
787 *a++ = le32toh(*p);
788 }
789
790 void
791 dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c)
792 {
793 panic("dino_rm_8: not implemented");
794 }
795
796 void
797 dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c)
798 {
799 volatile uint8_t *p;
800
801 h += o;
802 if (h & 0xf0000000)
803 p = (volatile uint8_t *)h;
804 else {
805 struct dino_softc *sc = v;
806 volatile struct dino_regs *r = sc->sc_regs;
807
808 r->pci_addr = h;
809 p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
810 }
811
812 while (c--)
813 *p = *a++;
814 }
815
816 void
817 dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c)
818 {
819 volatile uint16_t *p;
820
821 h += o;
822 if (h & 0xf0000000)
823 p = (volatile uint16_t *)h;
824 else {
825 struct dino_softc *sc = v;
826 volatile struct dino_regs *r = sc->sc_regs;
827
828 r->pci_addr = h;
829 p = (volatile uint16_t *)&r->pci_io_data;
830 if (h & 2)
831 p++;
832 }
833
834 while (c--)
835 *p = htole16(*a++);
836 }
837
838 void
839 dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c)
840 {
841 volatile uint32_t *p;
842
843 h += o;
844 if (h & 0xf0000000)
845 p = (volatile uint32_t *)h;
846 else {
847 struct dino_softc *sc = v;
848 volatile struct dino_regs *r = sc->sc_regs;
849
850 r->pci_addr = h;
851 p = (volatile uint32_t *)&r->pci_io_data;
852 }
853
854 while (c--)
855 *p = htole32(*a++);
856 }
857
858 void
859 dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c)
860 {
861 panic("dino_wm_8: not implemented");
862 }
863
864 void
865 dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c)
866 {
867 volatile uint8_t *p;
868
869 h += o;
870 if (h & 0xf0000000)
871 p = (volatile uint8_t *)h;
872 else {
873 struct dino_softc *sc = v;
874 volatile struct dino_regs *r = sc->sc_regs;
875
876 r->pci_addr = h;
877 p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
878 }
879
880 while (c--)
881 *p = vv;
882 }
883
884 void
885 dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c)
886 {
887 volatile uint16_t *p;
888
889 h += o;
890 if (h & 0xf0000000)
891 p = (volatile uint16_t *)h;
892 else {
893 struct dino_softc *sc = v;
894 volatile struct dino_regs *r = sc->sc_regs;
895
896 r->pci_addr = h;
897 p = (volatile uint16_t *)&r->pci_io_data;
898 if (h & 2)
899 p++;
900 }
901
902 while (c--)
903 *p = htole16(vv);
904 }
905
906 void
907 dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c)
908 {
909 volatile uint32_t *p;
910
911 h += o;
912 if (h & 0xf0000000)
913 p = (volatile uint32_t *)h;
914 else {
915 struct dino_softc *sc = v;
916 volatile struct dino_regs *r = sc->sc_regs;
917
918 r->pci_addr = h;
919 p = (volatile uint32_t *)&r->pci_io_data;
920 }
921
922 while (c--)
923 *p = htole32(vv);
924 }
925
926 void
927 dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c)
928 {
929 panic("dino_sm_8: not implemented");
930 }
931
932 void
933 dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o,
934 uint16_t *a, bus_size_t c)
935 {
936 volatile uint16_t *p;
937
938 h += o;
939 if (h & 0xf0000000)
940 p = (volatile uint16_t *)h;
941 else {
942 struct dino_softc *sc = v;
943 volatile struct dino_regs *r = sc->sc_regs;
944
945 r->pci_addr = h;
946 p = (volatile uint16_t *)&r->pci_io_data;
947 if (h & 2)
948 p++;
949 }
950
951 c /= 2;
952 while (c--)
953 *a++ = *p;
954 }
955
956 void
957 dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o,
958 uint32_t *a, bus_size_t c)
959 {
960 volatile uint32_t *p;
961
962 h += o;
963 if (h & 0xf0000000)
964 p = (volatile uint32_t *)h;
965 else {
966 struct dino_softc *sc = v;
967 volatile struct dino_regs *r = sc->sc_regs;
968
969 r->pci_addr = h;
970 p = (volatile uint32_t *)&r->pci_io_data;
971 }
972
973 c /= 4;
974 while (c--)
975 *a++ = *p;
976 }
977
978 void
979 dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o,
980 uint64_t *a, bus_size_t c)
981 {
982 panic("dino_rrm_8: not implemented");
983 }
984
985 void
986 dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o,
987 const uint16_t *a, bus_size_t c)
988 {
989 volatile uint16_t *p;
990
991 h += o;
992 if (h & 0xf0000000)
993 p = (volatile uint16_t *)h;
994 else {
995 struct dino_softc *sc = v;
996 volatile struct dino_regs *r = sc->sc_regs;
997
998 r->pci_addr = h;
999 p = (volatile uint16_t *)&r->pci_io_data;
1000 if (h & 2)
1001 p++;
1002 }
1003
1004 c /= 2;
1005 while (c--)
1006 *p = *a++;
1007 }
1008
1009 void
1010 dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o,
1011 const uint32_t *a, bus_size_t c)
1012 {
1013 volatile uint32_t *p;
1014
1015 h += o;
1016 if (h & 0xf0000000)
1017 p = (volatile uint32_t *)h;
1018 else {
1019 struct dino_softc *sc = v;
1020 volatile struct dino_regs *r = sc->sc_regs;
1021
1022 r->pci_addr = h;
1023 p = (volatile uint32_t *)&r->pci_io_data;
1024 }
1025
1026 c /= 4;
1027 while (c--)
1028 *p = *a++;
1029 }
1030
1031 void
1032 dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o,
1033 const uint64_t *a, bus_size_t c)
1034 {
1035 panic("dino_wrm_8: not implemented");
1036 }
1037
1038 void
1039 dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c)
1040 {
1041 volatile uint8_t *p;
1042
1043 h += o;
1044 if (h & 0xf0000000) {
1045 p = (volatile uint8_t *)h;
1046 while (c--)
1047 *a++ = *p++;
1048 } else {
1049 struct dino_softc *sc = v;
1050 volatile struct dino_regs *r = sc->sc_regs;
1051
1052 for (; c--; h++) {
1053 r->pci_addr = h;
1054 p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
1055 *a++ = *p;
1056 }
1057 }
1058 }
1059
1060 void
1061 dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c)
1062 {
1063 volatile uint16_t *p, data;
1064
1065 h += o;
1066 if (h & 0xf0000000) {
1067 p = (volatile uint16_t *)h;
1068 while (c--) {
1069 data = *p++;
1070 *a++ = le16toh(data);
1071 }
1072 } else {
1073 struct dino_softc *sc = v;
1074 volatile struct dino_regs *r = sc->sc_regs;
1075
1076 for (; c--; h += 2) {
1077 r->pci_addr = h;
1078 p = (volatile uint16_t *)&r->pci_io_data;
1079 if (h & 2)
1080 p++;
1081 data = *p;
1082 *a++ = le16toh(data);
1083 }
1084 }
1085 }
1086
1087 void
1088 dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c)
1089 {
1090 volatile uint32_t *p, data;
1091
1092 h += o;
1093 if (h & 0xf0000000) {
1094 p = (volatile uint32_t *)h;
1095 while (c--) {
1096 data = *p++;
1097 *a++ = le32toh(data);
1098 }
1099 } else {
1100 struct dino_softc *sc = v;
1101 volatile struct dino_regs *r = sc->sc_regs;
1102
1103 for (; c--; h += 4) {
1104 r->pci_addr = h;
1105 data = r->pci_io_data;
1106 *a++ = le32toh(data);
1107 }
1108 }
1109 }
1110
1111 void
1112 dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c)
1113 {
1114 panic("dino_rr_8: not implemented");
1115 }
1116
1117 void
1118 dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c)
1119 {
1120 volatile uint8_t *p;
1121
1122 h += o;
1123 if (h & 0xf0000000) {
1124 p = (volatile uint8_t *)h;
1125 while (c--)
1126 *p++ = *a++;
1127 } else {
1128 struct dino_softc *sc = v;
1129 volatile struct dino_regs *r = sc->sc_regs;
1130
1131 for (; c--; h++) {
1132 r->pci_addr = h;
1133 p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
1134 *p = *a++;
1135 }
1136 }
1137 }
1138
1139 void
1140 dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c)
1141 {
1142 volatile uint16_t *p, data;
1143
1144 h += o;
1145 if (h & 0xf0000000) {
1146 p = (volatile uint16_t *)h;
1147 while (c--) {
1148 data = *a++;
1149 *p++ = htole16(data);
1150 }
1151 } else {
1152 struct dino_softc *sc = v;
1153 volatile struct dino_regs *r = sc->sc_regs;
1154
1155 for (; c--; h += 2) {
1156 r->pci_addr = h;
1157 p = (volatile uint16_t *)&r->pci_io_data;
1158 if (h & 2)
1159 p++;
1160 data = *a++;
1161 *p = htole16(data);
1162 }
1163 }
1164 }
1165
1166 void
1167 dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c)
1168 {
1169 volatile uint32_t *p, data;
1170
1171 h += o;
1172 if (h & 0xf0000000) {
1173 p = (volatile uint32_t *)h;
1174 while (c--) {
1175 data = *a++;
1176 *p++ = htole32(data);
1177 }
1178 } else {
1179 struct dino_softc *sc = v;
1180 volatile struct dino_regs *r = sc->sc_regs;
1181
1182 for (; c--; h += 4) {
1183 r->pci_addr = h;
1184 data = *a++;
1185 r->pci_io_data = htole32(data);
1186 }
1187 }
1188 }
1189
1190 void
1191 dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c)
1192 {
1193 panic("dino_wr_8: not implemented");
1194 }
1195
1196 void
1197 dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o,
1198 uint16_t *a, bus_size_t c)
1199 {
1200 volatile uint16_t *p;
1201
1202 c /= 2;
1203 h += o;
1204 if (h & 0xf0000000) {
1205 p = (volatile uint16_t *)h;
1206 while (c--)
1207 *a++ = *p++;
1208 } else {
1209 struct dino_softc *sc = v;
1210 volatile struct dino_regs *r = sc->sc_regs;
1211
1212 for (; c--; h += 2) {
1213 r->pci_addr = h;
1214 p = (volatile uint16_t *)&r->pci_io_data;
1215 if (h & 2)
1216 p++;
1217 *a++ = *p;
1218 }
1219 }
1220 }
1221
1222 void
1223 dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o,
1224 uint32_t *a, bus_size_t c)
1225 {
1226 volatile uint32_t *p;
1227
1228 c /= 4;
1229 h += o;
1230 if (h & 0xf0000000) {
1231 p = (volatile uint32_t *)h;
1232 while (c--)
1233 *a++ = *p++;
1234 } else {
1235 struct dino_softc *sc = v;
1236 volatile struct dino_regs *r = sc->sc_regs;
1237
1238 for (; c--; h += 4) {
1239 r->pci_addr = h;
1240 *a++ = r->pci_io_data;
1241 }
1242 }
1243 }
1244
1245 void
1246 dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o,
1247 uint64_t *a, bus_size_t c)
1248 {
1249 panic("dino_rrr_8: not implemented");
1250 }
1251
1252 void
1253 dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o,
1254 const uint16_t *a, bus_size_t c)
1255 {
1256 volatile uint16_t *p;
1257
1258 c /= 2;
1259 h += o;
1260 if (h & 0xf0000000) {
1261 p = (volatile uint16_t *)h;
1262 while (c--)
1263 *p++ = *a++;
1264 } else {
1265 struct dino_softc *sc = v;
1266 volatile struct dino_regs *r = sc->sc_regs;
1267
1268 for (; c--; h += 2) {
1269 r->pci_addr = h;
1270 p = (volatile uint16_t *)&r->pci_io_data;
1271 if (h & 2)
1272 p++;
1273 *p = *a++;
1274 }
1275 }
1276 }
1277
1278 void
1279 dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o,
1280 const uint32_t *a, bus_size_t c)
1281 {
1282 volatile uint32_t *p;
1283
1284 c /= 4;
1285 h += o;
1286 if (h & 0xf0000000) {
1287 p = (volatile uint32_t *)h;
1288 while (c--)
1289 *p++ = *a++;
1290 } else {
1291 struct dino_softc *sc = v;
1292 volatile struct dino_regs *r = sc->sc_regs;
1293
1294 for (; c--; h += 4) {
1295 r->pci_addr = h;
1296 r->pci_io_data = *a++;
1297 }
1298 }
1299 }
1300
1301 void
1302 dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o,
1303 const uint64_t *a, bus_size_t c)
1304 {
1305 panic("dino_wrr_8: not implemented");
1306 }
1307
1308 void
1309 dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c)
1310 {
1311 volatile uint8_t *p;
1312
1313 h += o;
1314 if (h & 0xf0000000) {
1315 p = (volatile uint8_t *)h;
1316 while (c--)
1317 *p++ = vv;
1318 } else {
1319 struct dino_softc *sc = v;
1320 volatile struct dino_regs *r = sc->sc_regs;
1321
1322 for (; c--; h++) {
1323 r->pci_addr = h;
1324 p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
1325 *p = vv;
1326 }
1327 }
1328 }
1329
1330 void
1331 dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c)
1332 {
1333 volatile uint16_t *p;
1334
1335 h += o;
1336 vv = htole16(vv);
1337 if (h & 0xf0000000) {
1338 p = (volatile uint16_t *)h;
1339 while (c--)
1340 *p++ = vv;
1341 } else {
1342 struct dino_softc *sc = v;
1343 volatile struct dino_regs *r = sc->sc_regs;
1344
1345 for (; c--; h += 2) {
1346 r->pci_addr = h;
1347 p = (volatile uint16_t *)&r->pci_io_data;
1348 if (h & 2)
1349 p++;
1350 *p = vv;
1351 }
1352 }
1353 }
1354
1355 void
1356 dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c)
1357 {
1358 volatile uint32_t *p;
1359
1360 h += o;
1361 vv = htole32(vv);
1362 if (h & 0xf0000000) {
1363 p = (volatile uint32_t *)h;
1364 while (c--)
1365 *p++ = vv;
1366 } else {
1367 struct dino_softc *sc = v;
1368 volatile struct dino_regs *r = sc->sc_regs;
1369
1370 for (; c--; h += 4) {
1371 r->pci_addr = h;
1372 r->pci_io_data = vv;
1373 }
1374 }
1375 }
1376
1377 void
1378 dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c)
1379 {
1380 panic("dino_sr_8: not implemented");
1381 }
1382
1383 void
1384 dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1,
1385 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
1386 {
1387 while (c--)
1388 dino_w1(v, h1, o1++, dino_r1(v, h2, o2++));
1389 }
1390
1391 void
1392 dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1,
1393 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
1394 {
1395 while (c--) {
1396 dino_w2(v, h1, o1, dino_r2(v, h2, o2));
1397 o1 += 2;
1398 o2 += 2;
1399 }
1400 }
1401
1402 void
1403 dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1,
1404 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
1405 {
1406 while (c--) {
1407 dino_w4(v, h1, o1, dino_r4(v, h2, o2));
1408 o1 += 4;
1409 o2 += 4;
1410 }
1411 }
1412
1413 void
1414 dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1,
1415 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
1416 {
1417 while (c--) {
1418 dino_w8(v, h1, o1, dino_r8(v, h2, o2));
1419 o1 += 8;
1420 o2 += 8;
1421 }
1422 }
1423
1424
1425 const struct hppa_bus_space_tag dino_iomemt = {
1426 NULL,
1427
1428 NULL, dino_unmap, dino_subregion, NULL, dino_free,
1429 dino_barrier, dino_vaddr, dino_mmap,
1430 dino_r1, dino_r2, dino_r4, dino_r8,
1431 dino_w1, dino_w2, dino_w4, dino_w8,
1432 dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8,
1433 dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8,
1434 dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8,
1435 dino_rrm_2, dino_rrm_4, dino_rrm_8,
1436 dino_wrm_2, dino_wrm_4, dino_wrm_8,
1437 dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8,
1438 dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8,
1439 dino_rrr_2, dino_rrr_4, dino_rrr_8,
1440 dino_wrr_2, dino_wrr_4, dino_wrr_8,
1441 dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8,
1442 dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8
1443 };
1444
1445 int
1446 dino_dmamap_create(void *v, bus_size_t size, int nsegments,
1447 bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp)
1448 {
1449 struct dino_softc *sc = v;
1450
1451 /* TODO check the addresses, boundary, enable dma */
1452
1453 return bus_dmamap_create(sc->sc_dmat, size, nsegments,
1454 maxsegsz, boundary, flags, dmamp);
1455 }
1456
1457 void
1458 dino_dmamap_destroy(void *v, bus_dmamap_t map)
1459 {
1460 struct dino_softc *sc = v;
1461
1462 bus_dmamap_destroy(sc->sc_dmat, map);
1463 }
1464
1465 int
1466 dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size,
1467 struct proc *p, int flags)
1468 {
1469 struct dino_softc *sc = v;
1470
1471 return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags);
1472 }
1473
1474 int
1475 dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags)
1476 {
1477 struct dino_softc *sc = v;
1478
1479 return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags);
1480 }
1481
1482 int
1483 dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags)
1484 {
1485 struct dino_softc *sc = v;
1486
1487 return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags);
1488 }
1489
1490 int
1491 dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs,
1492 int nsegs, bus_size_t size, int flags)
1493 {
1494 struct dino_softc *sc = v;
1495
1496 return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags);
1497 }
1498
1499 void
1500 dino_dmamap_unload(void *v, bus_dmamap_t map)
1501 {
1502 struct dino_softc *sc = v;
1503
1504 bus_dmamap_unload(sc->sc_dmat, map);
1505 }
1506
1507 void
1508 dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off,
1509 bus_size_t len, int ops)
1510 {
1511 struct dino_softc *sc = v;
1512
1513 return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops);
1514 }
1515
1516 int
1517 dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment,
1518 bus_size_t boundary, bus_dma_segment_t *segs,
1519 int nsegs, int *rsegs, int flags)
1520 {
1521 struct dino_softc *sc = v;
1522
1523 return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary,
1524 segs, nsegs, rsegs, flags);
1525 }
1526
1527 void
1528 dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs)
1529 {
1530 struct dino_softc *sc = v;
1531
1532 bus_dmamem_free(sc->sc_dmat, segs, nsegs);
1533 }
1534
1535 int
1536 dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size,
1537 void **kvap, int flags)
1538 {
1539 struct dino_softc *sc = v;
1540
1541 return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags);
1542 }
1543
1544 void
1545 dino_dmamem_unmap(void *v, void *kva, size_t size)
1546 {
1547 struct dino_softc *sc = v;
1548
1549 bus_dmamem_unmap(sc->sc_dmat, kva, size);
1550 }
1551
1552 paddr_t
1553 dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off,
1554 int prot, int flags)
1555 {
1556 struct dino_softc *sc = v;
1557
1558 return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags);
1559 }
1560
1561 const struct hppa_bus_dma_tag dino_dmat = {
1562 NULL,
1563 dino_dmamap_create, dino_dmamap_destroy,
1564 dino_dmamap_load, dino_dmamap_load_mbuf,
1565 dino_dmamap_load_uio, dino_dmamap_load_raw,
1566 dino_dmamap_unload, dino_dmamap_sync,
1567
1568 dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map,
1569 dino_dmamem_unmap, dino_dmamem_mmap
1570 };
1571
1572 const struct hppa_pci_chipset_tag dino_pc = {
1573 NULL,
1574 dino_attach_hook, dino_maxdevs, dino_make_tag, dino_decompose_tag,
1575 dino_conf_read, dino_conf_write,
1576 dino_intr_map, dino_intr_string,
1577 dino_intr_establish, dino_intr_disestablish,
1578 #if NCARDBUS > 0
1579 dino_alloc_parent
1580 #else
1581 NULL
1582 #endif
1583 };
1584
1585 int
1586 dinomatch(device_t parent, cfdata_t cfdata, void *aux)
1587 {
1588 struct confargs *ca = aux;
1589
1590 /* there will be only one */
1591 if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE ||
1592 ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO)
1593 return 0;
1594
1595 /* Make sure we have an IRQ. */
1596 if (ca->ca_irq == HP700CF_IRQ_UNDEF)
1597 ca->ca_irq = hp700_intr_allocate_bit(&int_reg_cpu);
1598
1599 return 1;
1600 }
1601
1602 void
1603 dinoattach(device_t parent, device_t self, void *aux)
1604 {
1605 struct dino_softc *sc = device_private(self);
1606 struct confargs *ca = (struct confargs *)aux, nca;
1607 struct pcibus_attach_args pba;
1608 volatile struct dino_regs *r;
1609 const char *p;
1610 u_int data;
1611 int s, ver;
1612
1613 sc->sc_dv = self;
1614 sc->sc_bt = ca->ca_iot;
1615 sc->sc_dmat = ca->ca_dmatag;
1616
1617 if (ca->ca_irq == HP700CF_IRQ_UNDEF) {
1618 aprint_error_dev(self, ": can't allocate IRQ");
1619 return;
1620 }
1621
1622 if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) {
1623 aprint_error(": can't map space\n");
1624 return;
1625 }
1626
1627 sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh;
1628 #ifdef trust_the_firmware_to_proper_initialize_everything
1629 r->io_addr_en = 0;
1630 r->io_control = 0x80;
1631 r->pamr = 0;
1632 r->papr = 0;
1633 r->io_fbb_en |= 1;
1634 r->damode = 0;
1635 r->gmask &= ~1; /* allow GSC bus req */
1636 r->pciror = 0;
1637 r->pciwor = 0;
1638 r->brdg_feat = 0xc0000000;
1639 #endif
1640
1641 snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname),
1642 "%s_io", device_xname(self));
1643 if ((sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff,
1644 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_MALLOCOK)) == NULL) {
1645 aprint_error(": can't allocate I/O extent map\n");
1646 bus_space_unmap(sc->sc_bt, sc->sc_bh, PAGE_SIZE);
1647 return;
1648 }
1649
1650 /* interrupts guts */
1651 s = splhigh();
1652 r->icr = 0;
1653 r->imr = ~0;
1654 data = r->irr0;
1655 r->imr = 0;
1656 r->iar0 = cpu_gethpa(0) | (31 - ca->ca_irq);
1657 splx(s);
1658 /* Establish the interrupt register. */
1659 hp700_intr_reg_establish(&sc->sc_int_reg);
1660 sc->sc_int_reg.int_reg_mask = &r->imr;
1661 sc->sc_int_reg.int_reg_req = &r->irr0;
1662 sc->sc_int_reg.int_reg_level = &r->ilr;
1663 /* Add the I/O interrupt register. */
1664 sc->sc_int_reg.int_reg_dev = device_xname(self);
1665 sc->sc_ih = hp700_intr_establish(sc->sc_dv, IPL_NONE,
1666 NULL, &sc->sc_int_reg, &int_reg_cpu, ca->ca_irq);
1667
1668 /* TODO establish the bus error interrupt */
1669
1670 r->iodc = 0;
1671 data = r->iodc;
1672 ver = (ca->ca_type.iodc_model << 4) |
1673 (ca->ca_type.iodc_revision >> 4);
1674 switch (ver) {
1675 case 0x05d: p = "Dino"; /* j2240 */
1676 case 0x680: p = "Dino";
1677 switch (data >> 16) {
1678 case 0x6800: ver = 0x20; break;
1679 case 0x6801: ver = 0x21; break;
1680 case 0x6802: ver = 0x30; break;
1681 case 0x6803: ver = 0x31; break;
1682 default: ver = 0x40; break;
1683 }
1684 break;
1685
1686 case 0x682: p = "Cujo";
1687 switch (data >> 16) {
1688 case 0x6820: ver = 0x10; break;
1689 case 0x6821: ver = 0x20; break;
1690 default: ver = 0x30; break;
1691 }
1692 break;
1693
1694 default: p = "Mojo";
1695 ver = (data >> 16) & 0xff;
1696 break;
1697 }
1698 sc->sc_ver = ver;
1699 aprint_normal(": %s V%d.%d\n", p, ver >> 4, ver & 0xf);
1700
1701 sc->sc_iot = dino_iomemt;
1702 sc->sc_iot.hbt_cookie = sc;
1703 sc->sc_iot.hbt_map = dino_iomap;
1704 sc->sc_iot.hbt_alloc = dino_ioalloc;
1705 sc->sc_memt = dino_iomemt;
1706 sc->sc_memt.hbt_cookie = sc;
1707 sc->sc_memt.hbt_map = dino_memmap;
1708 sc->sc_memt.hbt_alloc = dino_memalloc;
1709 sc->sc_pc = dino_pc;
1710 sc->sc_pc._cookie = sc;
1711 sc->sc_dmatag = dino_dmat;
1712 sc->sc_dmatag._cookie = sc;
1713
1714 /* scan for ps2 kbd/ms, serial, and flying toasters */
1715 nca = *ca;
1716
1717 nca.ca_hpabase = 0;
1718 nca.ca_nmodules = MAXMODBUS;
1719 pdc_scanbus(self, &nca, dino_callback);
1720
1721 memset(&pba, 0, sizeof(pba));
1722 pba.pba_iot = &sc->sc_iot;
1723 pba.pba_memt = &sc->sc_memt;
1724 pba.pba_dmat = &sc->sc_dmatag;
1725 pba.pba_pc = &sc->sc_pc;
1726 pba.pba_bus = 0;
1727 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
1728 config_found_ia(self, "pcibus", &pba, pcibusprint);
1729 }
1730
1731 static void
1732 dino_callback(device_t self, struct confargs *ca)
1733 {
1734
1735 config_found_sm_loc(self, "dino", NULL, ca, mbprint, mbsubmatch);
1736 }
NetBSD on the FriendlyARM MINI2440