sys/arch/hp700/include/pdc.h

   1 /*      $NetBSD: pdc.h,v 1.10 2009/05/24 06:53:35 skrll Exp $   */
   2
   3 /*      $OpenBSD: pdc.h,v 1.35 2007/07/15 20:03:48 kettenis Exp $       */
   4
   5 /*
   6  * Copyright (c) 1990 mt Xinu, Inc.  All rights reserved.
   7  * Copyright (c) 1990,1991,1992,1994 University of Utah.  All rights reserved.
   8  *
   9  * Permission to use, copy, modify and distribute this software is hereby
  10  * granted provided that (1) source code retains these copyright, permission,
  11  * and disclaimer notices, and (2) redistributions including binaries
  12  * reproduce the notices in supporting documentation, and (3) all advertising
  13  * materials mentioning features or use of this software display the following
  14  * acknowledgement: ``This product includes software developed by the
  15  * Computer Systems Laboratory at the University of Utah.''
  16  *
  17  * Copyright (c) 1990 mt Xinu, Inc.
  18  * This file may be freely distributed in any form as long as
  19  * this copyright notice is included.
  20  * MTXINU, THE UNIVERSITY OF UTAH, AND CSL PROVIDE THIS SOFTWARE ``AS
  21  * IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
  22  * WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
  23  * FITNESS FOR A PARTICULAR PURPOSE.
  24  *
  25  * CSL requests users of this software to return to csl-dist@cs.utah.edu any
  26  * improvements that they make and grant CSL redistribution rights.
  27  *
  28  *      Utah $Hdr: pdc.h 1.12 94/12/14$
  29  *      Author: Jeff Forys (CSS), Dave Slattengren (mtXinu)
  30  */
  31
  32 #ifndef _MACHINE_PDC_H_
  33 #define _MACHINE_PDC_H_
  34
  35 /*
  36  * Definitions for interaction with "Processor Dependent Code",
  37  * which is a set of ROM routines used to provide information to the OS.
  38  * Also includes definitions for the layout of "Page Zero" memory when
  39  * boot code is invoked.
  40  *
  41  * Glossary:
  42  *      PDC:    Processor Dependent Code (ROM or copy of ROM).
  43  *      IODC:   I/O Dependent Code (module-type dependent code).
  44  *      IPL:    Boot program (loaded into memory from boot device).
  45  *      HPA:    Hard Physical Address (hardwired address).
  46  *      SPA:    Soft Physical Address (reconfigurable address).
  47  *
  48  *
  49  *
  50  *
  51  * Definitions for talking to IODC (I/O Dependent Code).
  52  *
  53  * The PDC is used to load I/O Dependent Code from a particular module.
  54  * I/O Dependent Code is module-type dependent software which provides
  55  * a uniform way to identify, initialize, and access a module (and in
  56  * some cases, their devices).
  57  */
  58
  59 /*
  60  * Our Initial Memory Module is laid out as follows.
  61  *
  62  *      0x000           +--------------------+
  63  *                      | Page Zero (iomod.h)|
  64  *      0x800           +--------------------+
  65  *                      |                    |
  66  *                      |                    |
  67  *                      |        PDC         |
  68  *                      |                    |
  69  *                      |                    |
  70  *      MEM_FREE        +--------------------+
  71  *                      |                    |
  72  *                      |    Console IODC    |
  73  *                      |                    |
  74  *      MEM_FREE+64k    +--------------------+
  75  *                      |                    |
  76  *                      |  Boot Device IODC  |
  77  *                      |                    |
  78  *      IPL_START       +--------------------+
  79  *                      |                    |
  80  *                      | IPL Code or Kernel |
  81  *                      |                    |
  82  *                      +--------------------+
  83  *
  84  * Restrictions:
  85  *      MEM_FREE (pagezero.mem_free) can be no greater than 32K.
  86  *      The PDC may use up to MEM_FREE + 32K (for Console & Boot IODC).
  87  *      IPL_START must be less than or equal to 64K.
  88  *
  89  * The IPL (boot) Code is immediately relocated to RELOC (check
  90  * "../stand/Makefile") to make way for the Kernel.
  91  */
  92
  93 #define IODC_MAXSIZE    (64 * 1024)     /* maximum size of IODC */
  94 #define IODC_MINIOSIZ   64              /* minimum buffer size for IODC call */
  95 #define IODC_MAXIOSIZ   (64 * 1024)     /* maximum buffer size for IODC call */
  96
  97 #define PDC_ALIGNMENT   __attribute__ ((__aligned__(64)))
  98 #define PDC_STACKSIZE   (2*NBPG)        /* PDC spec says 7K. */
  99
 100
 101 /*
 102  * The PDC Entry Points and their arguments...
 103  */
 104
 105 #define PDC_POW_FAIL    1       /* prepare for power failure */
 106 #define PDC_POW_FAIL_DFLT       0
 107
 108 #define PDC_CHASSIS     2       /* update chassis display (see below) */
 109 #define PDC_CHASSIS_DISP        0       /* update display */
 110 #define PDC_CHASSIS_WARN        1       /* return warnings */
 111 #define PDC_CHASSIS_ALL         2       /* update display & return warnings */
 112 #define PDC_CHASSIS_INFO        128     /* return led/lcd info */
 113
 114 #define PDC_PIM         3       /* access Processor Internal Memory */
 115 #define PDC_PIM_HPMC            0       /* read High Pri Mach Chk data */
 116 #define PDC_PIM_SIZE            1       /* return size */
 117 #define PDC_PIM_LPMC            2       /* read Low Pri Mach Chk data */
 118 #define PDC_PIM_SBD             3       /* read soft boot data */
 119 #define PDC_PIM_TOC             4       /* read TOC data (used to use HPMC) */
 120
 121 #define PDC_MODEL       4       /* processor model number info */
 122 #define PDC_MODEL_INFO          0       /* processor model number info */
 123 #define PDC_MODEL_BOOTID        1       /* set BOOT_ID of processor */
 124 #define PDC_MODEL_COMP          2       /* return component version numbers */
 125 #define PDC_MODEL_MODEL         3       /* return system model information */
 126 #define PDC_MODEL_ENSPEC        4       /* enable product-specific instrs */
 127 #define PDC_MODEL_DISPEC        5       /* disable product-specific instrs */
 128 #define PDC_MODEL_CPUID         6       /* return CPU versions */
 129 #define PDC_MODEL_CPBALITIES    7       /* return capabilites */
 130 #define PDC_MODEL_GETBOOTSTOPTS 8       /* return boot test options */
 131 #define PDC_MODEL_SETBOOTSTOPTS 9       /* set boot test options */
 132
 133 #define PDC_CACHE       5       /* return cache and TLB params */
 134 #define PDC_CACHE_DFLT          0       /* return parameters */
 135 #define PDC_CACHE_SETCS         1       /* set coherence state */
 136 #define PDC_CACHE_GETSPIDB      2       /* get space-id bits */
 137
 138 #define PDC_HPA         6       /* return HPA of processor */
 139 #define PDC_HPA_DFLT            0
 140 #define PDC_HPA_MODULES         1
 141
 142 #define PDC_COPROC      7       /* return co-processor configuration */
 143 #define PDC_COPROC_DFLT         0
 144
 145 #define PDC_IODC        8       /* talk to IODC */
 146 #define PDC_IODC_READ           0       /* read IODC entry point */
 147 #define         IODC_DATA       0       /* get first 16 bytes from mod IODC */
 148 #define         IODC_INIT       3       /* initialize (see options below) */
 149 #define         IODC_INIT_FIRST 2       /* find first device on module */
 150 #define         IODC_INIT_NEXT  3       /* find subsequent devices on module */
 151 #define         IODC_INIT_ALL   4       /* initialize module and device */
 152 #define         IODC_INIT_DEV   5       /* initialize device */
 153 #define         IODC_INIT_MOD   6       /* initialize module */
 154 #define         IODC_INIT_MSG   9       /* return error message(s) */
 155 #define         IODC_INIT_STR   20      /* find device w/ spec in string */
 156 #define         IODC_IO         4       /* perform I/O (see options below) */
 157 #define         IODC_IO_READ    0       /* read from boot device */
 158 #define         IODC_IO_WRITE   1       /* write to boot device */
 159 #define         IODC_IO_CONSIN  2       /* read from console */
 160 #define         IODC_IO_CONSOUT 3       /* write to conosle */
 161 #define         IODC_IO_CLOSE   4       /* close device */
 162 #define         IODC_IO_MSG     9       /* return error message(s) */
 163 #define         IODC_SPA        5       /* get extended SPA information */
 164 #define         IODC_SPA_DFLT   0       /* return SPA information */
 165 #define         IODC_TEST       8       /* perform self tests */
 166 #define         IODC_TEST_INFO  0       /* return test information */
 167 #define         IODC_TEST_STEP  1       /* execute a particular test */
 168 #define         IODC_TEST_TEST  2       /* describe a test section */
 169 #define         IODC_TEST_MSG   9       /* return error message(s) */
 170 #define PDC_IODC_NINIT          2       /* non-destructive init */
 171 #define PDC_IODC_DINIT          3       /* destructive init */
 172 #define PDC_IODC_MEMERR         4       /* check for memory errors */
 173 #define PDC_IODC_IMEMMASTER     5       /* interlieved memory master ID */
 174
 175 #define PDC_TOD         9       /* access time-of-day clock */
 176 #define PDC_TOD_READ            0       /* read TOD clock */
 177 #define PDC_TOD_WRITE           1       /* write TOD clock */
 178 #define PDC_TOD_ITIMER          2       /* calibrate Interval Timer (CR16) */
 179
 180 #define PDC_STABLE      10      /* access Stable Storage (SS) */
 181 #define PDC_STABLE_READ         0       /* read SS */
 182 #define PDC_STABLE_WRITE        1       /* write SS */
 183 #define PDC_STABLE_SIZE         2       /* return size of SS */
 184 #define PDC_STABLE_VRFY         3       /* verify contents of SS */
 185 #define PDC_STABLE_INIT         4       /* initialize SS */
 186
 187 #define PDC_NVM         11      /* access Non-Volatile Memory (NVM) */
 188 #define PDC_NVM_READ            0       /* read NVM */
 189 #define PDC_NVM_WRITE           1       /* write NVM */
 190 #define PDC_NVM_SIZE            2       /* return size of NVM */
 191 #define PDC_NVM_VRFY            3       /* verify contents of NVM */
 192 #define PDC_NVM_INIT            4       /* initialize NVM */
 193
 194 #define PDC_ADD_VALID   12      /* check address for validity */
 195 #define PDC_ADD_VALID_DFLT      0
 196
 197 #define PDC_BUS_BAD     13      /* verify Error Detection Circuitry (EDC) */
 198 #define PDC_BUS_BAD_DLFT        0
 199
 200 #define PDC_DEBUG       14      /* return address of PDC debugger */
 201 #define PDC_DEBUG_DFLT          0
 202
 203 #define PDC_INSTR       15      /* return instr that invokes PDCE_CHECK */
 204 #define PDC_INSTR_DFLT          0
 205
 206 #define PDC_PROC        16      /* stop currently executing processor */
 207 #define PDC_PROC_STOP           0
 208 #define PDC_PROC_RENDEZVOUS     1
 209
 210 #define PDC_CONF        17      /* (de)configure a module */
 211 #define PDC_CONF_DECONF         0       /* deconfigure module */
 212 #define PDC_CONF_RECONF         1       /* reconfigure module */
 213 #define PDC_CONF_INFO           2       /* get config informaion */
 214
 215 #define PDC_BLOCK_TLB   18      /* Manage Block TLB entries (BTLB) */
 216 #define PDC_BTLB_DEFAULT        0       /* Return BTLB configuration info  */
 217 #define PDC_BTLB_INSERT         1       /* Insert a BTLB entry             */
 218 #define PDC_BTLB_PURGE          2       /* Purge a BTLB entry              */
 219 #define PDC_BTLB_PURGE_ALL      3       /* Purge all BTLB entries          */
 220
 221 #define PDC_TLB         19      /* Manage Hardware TLB handling */
 222 #define PDC_TLB_INFO            0       /* Return HW-TLB configuration info  */
 223 #define PDC_TLB_CONFIG          1       /* Set HW-TLB pdir base and size */
 224
 225 #define PDC_TLB_CURRPDE         1       /* cr28 points to current pde on miss */
 226 #define PDC_TLB_RESERVD         3       /* reserved */
 227 #define PDC_TLB_NEXTPDE         5       /* cr28 points to next pde on miss */
 228 #define PDC_TLB_WORD3           7       /* cr28 is word 3 of 16 byte pde */
 229
 230 #define PDC_PSW         21      /* manage default values of configurable psw bits */
 231 #define PDC_PSW_GETMASK         0       /* get mask */
 232 #define PDC_PSW_DEFAULTS        1       /* get default bits values */
 233 #define PDC_PSW_SETDEFAULTS     2       /* set default bits values */
 234
 235 #define PDC_SYSTEM_MAP          22      /* map system modules */
 236 #define PDC_SYSTEM_MAP_FIND_MOD 0       /* find module by index */
 237 #define PDC_SYSTEM_MAP_FIND_ADDR        1       /* fetch list of addresses */
 238 #define PDC_SYSTEM_MAP_TRANS_PATH       2       /* get hpa from devpath */
 239
 240 #define PDC_SOFT_POWER          23      /* support for soft power switch */
 241 #define PDC_SOFT_POWER_INFO     0       /* get info about soft power switch */
 242 #define PDC_SOFT_POWER_ENABLE   1       /* enable/disable soft power switch */
 243
 244 #define PDC_PAT_CELL    64      /* cell operations */
 245 #define PDC_PAT_CELL_GETID      0       /* get cell id number */
 246 #define PDC_PAT_CELL_GETINFO    1       /* get cell info */
 247 #define PDC_PAT_CELL_MODULE     2       /* get module info */
 248 #define         PDC_PAT_IOVIEW  0
 249 #define         PDC_PAT_PAVIEW  1
 250
 251 #define PDC_PAT_CHASSIS 65      /* chassis log ops */
 252 #define PDC_PAT_CHASSIS_WRITE   0
 253 #define PDC_PAT_CHASSIS_READ    1
 254
 255 #define PDC_PAT_CPU     67
 256
 257 #define PDC_PAT_EVENT   68
 258
 259 #define PDC_PAT_HPMC    70
 260
 261 #define PDC_PAT_IO              71      /* online services for IO modules */
 262 #define PDC_PAT_IO_GET_PCI_RTSZ 15
 263 #define PDC_PAT_IO_GET_PCI_RT   16
 264
 265 #define PDC_PAT_MEM     72
 266
 267 #define PDC_PAT_NVRAM   73
 268
 269 #define PDC_PAT_PROTDOM 74
 270
 271 #define PDC_MEMMAP              128     /* hp700: return page information */
 272 #define PDC_MEMMAP_HPA          0       /* map module # to HPA */
 273
 274 #define PDC_EEPROM              129     /* Hversion dependent */
 275 #define PDC_EEPROM_READ_WORD    0
 276 #define PDC_EEPROM_WRITE_WORD   1
 277 #define PDC_EEPROM_READ_BYTE    2
 278 #define PDC_EEPROM_WRITE_BYTE   3
 279
 280 #define PDC_IO          135
 281 #define PDC_IO_READ_AND_CLEAR_ERRORS    0
 282 #define PDC_IO_RESET                    1
 283 #define PDC_IO_RESET_DEVICES            2
 284
 285 #define PDC_BROADCAST_RESET     136
 286 #define PDC_DO_RESET            0
 287 #define PDC_DO_FIRM_TEST_RESET  1
 288 #define PDC_BR_RECONFIGURATION  2
 289
 290 #define PDC_LAN_STATION_ID      138     /* Hversion dependent mechanism for */
 291 #define PDC_LAN_STATION_ID_READ 0       /* getting the lan station address  */
 292
 293 #define PDC_PCI_INDEX           147     /* PCI rt access */
 294 #define PDC_PCI_GET_INT_TBL_SZ  13
 295 #define PDC_PCI_GET_INT_TBL     14
 296
 297 #define PDC_ERR_OK              0       /* operation complete */
 298 #define PDC_ERR_WARNING         3       /* OK, but warning */
 299 #define PDC_ERR_NOPROC          -1      /* no such procedure */
 300 #define PDC_ERR_NOPT            -2      /* no such option */
 301 #define PDC_ERR_COMPL           -3      /* unable to complete w/o error */
 302 #define PDC_ERR_EOD             -9      /* end of device list */
 303 #define PDC_ERR_INVAL           -10     /* invalid argument */
 304 #define PDC_ERR_PFAIL           -12     /* aborted by powerfail */
 305
 306 #if !defined(_LOCORE)
 307
 308 struct iomod;
 309
 310 typedef int (*pdcio_t)(int, int, ...);
 311 typedef int (*iodcio_t)(struct iomod *, int, ...);
 312
 313 /*
 314  * Commonly used PDC calls and the structures they return.
 315  */
 316
 317 /*
 318  * Device path specifications used by PDC.
 319  */
 320 struct device_path {
 321         u_char  dp_flags;       /* see bit definitions below */
 322 #define PZF_AUTOBOOT    0x80    /* These two are PDC flags for how to locate */
 323 #define PZF_AUTOSEARCH  0x40    /*      the "boot device" */
 324 #define PZF_TIMER       0x0f    /* power of 2 # secs "boot timer" (0 == dflt) */
 325 #define PZF_BITS        "\020\010autoboot\07autosearch"
 326
 327         char    dp_bc[6];       /* Bus Converter routing info to a specific */
 328                                 /* I/O adaptor (< 0 means none, > 63 resvd) */
 329         char    dp_mod;         /* fixed field of specified module */
 330         int     dp_layers[6];   /* device-specific info (ctlr #, unit # ...) */
 331 #define PZL_BITS(l)     (((l) & 0x03) + 5)
 332 #define PZL_PARITY(l)   (((l) & 0x18) >> 3)
 333 #define PZL_SPEED(l)    (((l) & 0x3c0) >> 6)
 334 #define PZL_ENCODE(bits, parity, speed) \
 335         (((bits) - 5) & 0x03) | (((parity) & 0x3) << 3) | \
 336         (((speed) & 0x0f) << 6)
 337
 338 };
 339
 340 struct pdc_pim {        /* PDC_PIM */
 341         u_int   count;          /* actual (HPMC, LPMC) or total (SIZE) count */
 342         u_int   archsize;       /* size of architected regions (see "pim.h") */
 343         u_int   filler[30];
 344 };
 345
 346 struct pdc_model {      /* PDC_MODEL */
 347         u_int   hvers;          /* hardware version */
 348         u_int   rev : 4;        /* zero for all native processors */
 349         u_int   model : 20;     /* 4 for all native processors */
 350         u_int   sh : 1;         /* shadow registers are present */
 351         u_int   reserved : 2;   /* reserved */
 352         u_int   mc : 1;         /* module category (A - 0, B - 1) */
 353         u_int   reserved1 : 2;  /* reserved */
 354         u_int   pa_lvl : 2;     /* PA-RISC level */
 355         u_int   hw_id;          /* unique processor hardware identifier */
 356         u_int   boot_id;        /* same as hw_id */
 357         u_int   sw_id;          /* software security and licensing */
 358         u_int   sw_cap;         /* OS capabilities of processor */
 359         u_int   arch_rev;       /* architecture revision */
 360         u_int   pot_key;        /* potential key */
 361         u_int   curr_key;       /* current key */
 362         int     filler1;
 363         u_int   filler2[22];
 364 };
 365
 366 struct pdc_cpuid {      /* PDC_MODEL, PDC_CPUID */
 367         u_int   reserved : 20;
 368         u_int   version  :  7;  /* CPU version */
 369         u_int   revision :  5;  /* CPU revision */
 370         u_int   filler[31];
 371 };
 372
 373 struct pdc_getbootopts {        /* PDC_MODEL_GETBOOTOPTS */
 374         u_int   cur_test;       /* current enabled tests */
 375         u_int   sup_test;       /* supported tests */
 376         u_int   def_test;       /* default enabled tests */
 377         u_int   filler[29];
 378 };
 379
 380 struct cache_cf {       /* PDC_CACHE (for "struct pdc_cache") */
 381         u_int   cc_alias: 4,    /* virtual address aliasing boundary */
 382                 cc_block: 4,    /* used to determine most efficient stride */
 383                 cc_line : 3,    /* max data written by store (16-byte mults) */
 384                 cc_resv1: 2,    /* (reserved) */
 385                 cc_wt   : 1,    /* D-cache: write-to = 0, write-through = 1 */
 386                 cc_sh   : 2,    /* separate I and D = 0, shared I and D = 1 */
 387                 cc_cst  : 3,    /* D-cache: incoherent = 0, coherent = 1 */
 388                 cc_resv2:11,    /* (reserved) */
 389                 cc_hvers: 2;    /* H-VERSION dependent */
 390 };
 391
 392 struct itlb_cf {                /* PDC_CACHE (for "struct pdc_cache") */
 393         u_int   tc_resv1:12,    /* (reserved) */
 394                 tc_sh   : 2,    /* separate I and D = 0, shared I and D = 1 */
 395                 tc_hvers: 1,    /* H-VERSION dependent */
 396                 tc_page : 1,    /* 2K page size = 0, 4k page size = 1 */
 397                 tc_cst  : 3,    /* incoherent = 0, coherent = 1 */
 398                 tc_aid  : 5,    /* access id width = 15 + aid */
 399                 tc_sr   : 6,    /* space id width */
 400                 tc_hv2  : 2;    /* H-VERSION dependent */
 401 };
 402
 403 struct dtlb_cf {                /* PDC_CACHE (for "struct pdc_cache") */
 404         u_int   tc_resv1:12,    /* (reserved) */
 405                 tc_sh   : 2,    /* separate I and D = 0, shared I and D = 1 */
 406                 tc_hvers: 1,    /* H-VERSION dependent */
 407                 tc_u    : 1,    /* TLB U bit implemented  */
 408                 tc_cst  : 3,    /* incoherent = 0, coherent = 1 */
 409                 tc_resv2: 11,   /* (reserved) */
 410                 tc_hv2  : 2;    /* H-VERSION dependent */
 411 };
 412
 413 struct pdc_cache {      /* PDC_CACHE */
 414 /* Instruction cache */
 415         u_int   ic_size;        /* size of I-cache (in bytes) */
 416         struct cache_cf ic_conf;/* cache configuration (see above) */
 417         u_int   ic_base;        /* start addr of I-cache (for FICE flush) */
 418         u_int   ic_stride;      /* addr incr per i_count iteration (flush) */
 419         u_int   ic_count;       /* number of i_loop iterations (flush) */
 420         u_int   ic_loop;        /* number of FICE's per addr stride (flush) */
 421 /* Data cache */
 422         u_int   dc_size;        /* size of D-cache (in bytes) */
 423         struct cache_cf dc_conf;/* cache configuration (see above) */
 424         u_int   dc_base;        /* start addr of D-cache (for FDCE flush) */
 425         u_int   dc_stride;      /* addr incr per d_count iteration (flush) */
 426         u_int   dc_count;       /* number of d_loop iterations (flush) */
 427         u_int   dc_loop;        /* number of FDCE's per addr stride (flush) */
 428 /* Instruction TLB */
 429         u_int   it_size;        /* number of entries in I-TLB */
 430         struct itlb_cf it_conf; /* I-TLB configuration (see above) */
 431         u_int   it_sp_base;     /* start space of I-TLB (for PITLBE flush) */
 432         u_int   it_sp_stride;   /* space incr per sp_count iteration (flush) */
 433         u_int   it_sp_count;    /* number of off_count iterations (flush) */
 434         u_int   it_off_base;    /* start offset of I-TLB (for PITLBE flush) */
 435         u_int   it_off_stride;  /* offset incr per off_count iteration (flush)*/
 436         u_int   it_off_count;   /* number of it_loop iterations/space (flush) */
 437         u_int   it_loop;        /* number of PITLBE's per off_stride (flush) */
 438 /* Data TLB */
 439         u_int   dt_size;        /* number of entries in D-TLB */
 440         struct dtlb_cf dt_conf; /* D-TLB configuration (see above) */
 441         u_int   dt_sp_base;     /* start space of D-TLB (for PDTLBE flush) */
 442         u_int   dt_sp_stride;   /* space incr per sp_count iteration (flush) */
 443         u_int   dt_sp_count;    /* number of off_count iterations (flush) */
 444         u_int   dt_off_base;    /* start offset of D-TLB (for PDTLBE flush) */
 445         u_int   dt_off_stride;  /* offset incr per off_count iteration (flush)*/
 446         u_int   dt_off_count;   /* number of dt_loop iterations/space (flush) */
 447         u_int   dt_loop;        /* number of PDTLBE's per off_stride (flush) */
 448         u_int   filler[2];
 449 };
 450
 451 struct pdc_spidb {      /* PDC_CACHE, PDC_CACHE_GETSPIDB */
 452         u_int   spidR1   : 4;
 453         u_int   spidbits : 12;
 454         u_int   spidR2   : 16;
 455         u_int   filler[31];
 456 };
 457
 458 struct pdc_cst {
 459         u_int   cstR1  : 16;
 460         u_int   cst    :  3;
 461         u_int   cstR2  : 13;
 462 };
 463
 464 struct pdc_coherence {  /* PDC_CACHE, PDC_CACHE_SETCS */
 465         struct pdc_cst  ia;
 466 #define ia_cst ia.cst
 467         struct pdc_cst  da;
 468 #define da_cst da.cst
 469         struct pdc_cst  ita;
 470 #define ita_cst ita.cst
 471         struct pdc_cst  dta;
 472 #define dta_cst dta.cst
 473         u_int   filler[28];
 474 };
 475
 476 struct pdc_hpa {        /* PDC_HPA */
 477         hppa_hpa_t hpa; /* HPA of processor */
 478         int     filler1;
 479         u_int   filler2[30];
 480 };
 481
 482 struct pdc_coproc {     /* PDC_COPROC */
 483         u_int   ccr_enable;     /* same format as CCR (CR 10) */
 484         u_int   ccr_present;    /* which co-proc's are present (bitset) */
 485         u_int   pad[15];
 486         u_int   fpu_revision;
 487         u_int   fpu_model;
 488         u_int   filler2[13];
 489 };
 490
 491 struct pdc_tod {        /* PDC_TOD, PDC_TOD_READ */
 492         u_int   sec;            /* elapsed time since 00:00:00 GMT, 1/1/70 */
 493         u_int   usec;           /* accurate to microseconds */
 494         u_int   filler2[30];
 495 };
 496
 497 struct pdc_itimer {     /* PDC_TOD_ITIMER */
 498         u_int   calib0;         /* double giving itmr freq */
 499         u_int   calib1;
 500         u_int   tod_acc;        /* TOD accuracy in 1e-9 part */
 501         u_int   cr_acc;         /* itmr accuracy in 1e-9 parts */
 502         u_int   filler[28];
 503 };
 504
 505 struct pdc_nvm {        /* PDC_NVM */
 506         u_int   hv[9];          /* 0x00: HV dependent */
 507         struct device_path bootpath;    /* 0x24: boot path */
 508         u_int   isl_ver;        /* 0x44: ISL revision */
 509         u_int   timestamp;      /* 0x48: timestamp */
 510         u_int   lif_ue[12];     /* 0x4c: LIF utility entries */
 511         u_int   eptr;           /* 0x7c: entry pointer */
 512         u_int   os_panic[32];   /* 0x80: OS panic info */
 513 };
 514
 515 struct pdc_instr {      /* PDC_INSTR */
 516         u_int   instr;          /* instruction that invokes PDC mchk entry pt */
 517         int     filler1;
 518         u_int   filler2[30];
 519 };
 520
 521 struct pdc_iodc_read {  /* PDC_IODC, PDC_IODC_READ */
 522         int     size;           /* number of bytes in selected entry point */
 523         int     filler1;
 524         u_int   filler2[30];
 525 };
 526
 527 struct pdc_iodc_minit { /* PDC_IODC, PDC_IODC_NINIT or PDC_IODC_DINIT */
 528         u_int   stat;           /* HPA.io_status style error returns */
 529         u_int   max_spa;        /* size of SPA (in bytes) > max_mem+map_mem */
 530         u_int   max_mem;        /* size of "implemented" memory (in bytes) */
 531         u_int   map_mem;        /* size of "mappable-only" memory (in bytes) */
 532         u_int   filler[28];
 533 };
 534
 535 struct btlb_info {              /* for "struct pdc_btlb" (PDC_BTLB) */
 536         u_int   resv0: 8,       /* (reserved) */
 537                 num_i: 8,       /* Number of instruction slots */
 538                 num_d: 8,       /* Number of data slots */
 539                 num_c: 8;       /* Number of combined slots */
 540 };
 541
 542 struct pdc_btlb {       /* PDC_BLOCK_TLB */
 543         u_int   min_size;       /* Min size in pages */
 544         u_int   max_size;       /* Max size in pages */
 545         struct btlb_info finfo; /* Fixed range info */
 546         struct btlb_info vinfo; /* Variable range info */
 547         u_int   filler[28];
 548 };
 549
 550 struct pdc_hwtlb {      /* PDC_TLB */
 551         u_int   min_size;       /* What do these mean? */
 552         u_int   max_size;
 553         u_int   filler[30];
 554 };
 555
 556 struct pdc_power_info {         /* PDC_SOFT_POWER_INFO */
 557         u_int   addr;           /* power register address */
 558         u_int   filler[31];
 559 };
 560
 561 struct pdc_pat_cell_id {        /* PDC_PAT_CELL_GETID */
 562         u_long  id;             /* cell id */
 563         u_long  loc;            /* cell location */
 564         u_long  filler[14];
 565 };
 566
 567 struct pdc_pat_cell_module {    /* PDC_PAT_CELL_MODULE */
 568         u_long  chpa;           /* config space HPA */
 569         u_long  info;           /* module info */
 570 #define PDC_PAT_CELL_MODTYPE(t) (((t) >> 56) & 0xff)
 571 #define PDC_PAT_CELL_MODDVI(t)  (((t) >> 48) & 0xff)
 572 #define PDC_PAT_CELL_MODIOC(t)  (((t) >> 40) & 0xff)
 573 #define PDC_PAT_CELL_MODSIZE(t) (((t) & 0xffffff) << PAGE_SHIFT)
 574         u_long  loc;            /* module location */
 575         struct device_path dp;  /* module path */
 576         u_long  pad[508];       /* cell module gedoens */
 577 };
 578
 579 struct pdc_pat_io_num { /* PDC_PAT_IO */
 580         u_int   num;
 581         u_int   filler[31];
 582 };
 583
 584 struct pdc_pat_pci_rt { /* PDC_PAT_IO_GET_PCI_RT */
 585         uint8_t         type;           /* 0x8b */
 586         uint8_t         len;
 587         uint8_t         itype;          /* 0 -- vectored int */
 588         uint8_t         trigger;        /* polarity/level */
 589         uint8_t         pin;            /* PCI pin number */
 590         uint8_t         bus;
 591         uint8_t         seg;            /* reserved */
 592         uint8_t         line;
 593         uint64_t        addr;           /* io sapic address */
 594 };
 595
 596 struct pdc_memmap {     /* PDC_MEMMAP */
 597         u_int   hpa;            /* HPA for module */
 598         u_int   morepages;      /* additional IO pages */
 599         u_int   filler[30];
 600 };
 601
 602 struct pdc_system_map_find_mod {        /* PDC_SYSTEM_MAP_FIND_MOD */
 603         u_int   hpa;
 604         u_int   size;           /* pages */
 605         u_int   naddrs;
 606         u_int   mod_index;
 607         u_int   filler[28];
 608 };
 609
 610 struct pdc_system_map_find_addr {       /* PDC_SYSTEM_MAP_FIND_ADDR */
 611         u_int   hpa;
 612         u_int   size;           /* pages */
 613         u_int   filler[30];
 614 };
 615
 616 struct pdc_lan_station_id {     /* PDC_LAN_STATION_ID */
 617         uint8_t addr[6];
 618         uint8_t filler1[2];
 619         u_int   filler2[30];
 620 };
 621
 622 /*
 623  * The PDC_CHASSIS is a strange bird.  The format for updating the display
 624  * is as follows:
 625  *
 626  *      0     11 12      14    15   16    19 20    23 24    27 28    31
 627  *      +-------+----------+-------+--------+--------+--------+--------+
 628  *      |   R   | OS State | Blank |  Hex1  |  Hex2  |  Hex3  |  Hex4  |
 629  *      +-------+----------+-------+--------+--------+--------+--------+
 630  *
 631  * Unfortunately, someone forgot to tell the hardware designers that
 632  * there was supposed to be a hex display somewhere.  The result is,
 633  * you can only toggle 5 LED's and the fault light.
 634  *
 635  * Interesting values for Hex1-Hex4 and the resulting LED displays:
 636  *
 637  *      FnFF                    CnFF:
 638  *       0      - - - - -               Counts in binary from 0x0 - 0xF
 639  *       2      o - - - -               for corresponding values of `n'.
 640  *       4      o o - - -
 641  *       6      o o o - -
 642  *       8      o o o o -
 643  *       A      o o o o o
 644  *
 645  * If the "Blank" bit is set, the display should be made blank.
 646  * The values for "OS State" are defined below.
 647  */
 648
 649 #define PDC_CHASSIS_BAR 0xF0FF  /* create a bar graph with LEDs */
 650 #define PDC_CHASSIS_CNT 0xC0FF  /* count with LEDs */
 651
 652 #define PDC_OSTAT(os)   (((os) & 0x7) << 17)
 653 #define PDC_OSTAT_OFF   0x0     /* all off */
 654 #define PDC_OSTAT_FAULT 0x1     /* the red LED of death */
 655 #define PDC_OSTAT_TEST  0x2     /* self test */
 656 #define PDC_OSTAT_BOOT  0x3     /* boot program running */
 657 #define PDC_OSTAT_SHUT  0x4     /* shutdown in progress */
 658 #define PDC_OSTAT_WARN  0x5     /* battery dying, etc */
 659 #define PDC_OSTAT_RUN   0x6     /* OS running */
 660 #define PDC_OSTAT_ON    0x7     /* all on */
 661
 662 struct pdc_chassis_info {
 663         u_int   size;
 664         u_int   max_size;
 665         u_int   filler[30];
 666 };
 667
 668 struct pdc_chassis_lcd {
 669         u_int   model : 16,
 670                 width : 16;
 671         u_int   cmd_addr;
 672         u_int   data_addr;
 673         u_int   delay;
 674         uint8_t line[2];
 675         uint8_t enabled;
 676         uint8_t heartbeat[3];
 677         uint8_t disk[3];
 678         u_int   filler[25];
 679 };
 680
 681 /*
 682  * A processors Stable Storage is accessed through the PDC.  There are
 683  * at least 96 bytes of stable storage (the device path information may
 684  * or may not exist).  However, as far as I know, processors provide at
 685  * least 192 bytes of stable storage.
 686  */
 687 struct stable_storage {
 688         struct device_path ss_pri_boot; /* (see above) */
 689         char    ss_filenames[32];
 690         u_short ss_os_version;  /* 0 == none, 1 == HP-UX, 2 == MPE-XL */
 691         char    ss_os[22];      /* OS-dependant information */
 692         char    ss_pdc[7];      /* reserved */
 693         char    ss_fast_size;   /* how much memory to test.  0xf == all, or */
 694                                 /*      else it's (256KB << ss_fast_size) */
 695         struct device_path ss_console;
 696         struct device_path ss_alt_boot;
 697         struct device_path ss_keyboard;
 698 };
 699
 700 /*
 701  * Recoverable error indications provided to boot code by the PDC.
 702  * Any non-zero value indicates error.
 703  */
 704 struct boot_err {
 705         u_int   be_resv : 10,   /* (reserved) */
 706                 be_fixed : 6,   /* module that produced error */
 707                 be_chas : 16;   /* error code (interpret as 4 hex digits) */
 708 };
 709
 710 #define HPBE_HBOOT_CORRECTABLE  0       /* hard-boot corrctable error */
 711 #define HPBE_HBOOT_UNCORRECTBL  1       /* hard-boot uncorrectable error */
 712 #define HPBE_SBOOT_CORRECTABLE  2       /* soft-boot correctable error */
 713 #define HPBE_SBOOT_UNCORRECTBL  3       /* soft-boot uncorrectable error */
 714 #define HPBE_ETEST_MODUNUSABLE  4       /* ENTRY_TEST err: module's unusable */
 715 #define HPBE_ETEST_MODDEGRADED  5       /* ENTRY_TEST err: module in degraded mode */
 716
 717
 718 /*
 719  * The PDC uses the following structure to completely define an I/O
 720  * module and the interface to its IODC.
 721  */
 722 typedef
 723 struct pz_device {
 724         struct device_path pz_dp;
 725 #define pz_flags        pz_dp.dp_flags
 726 #define pz_bc           pz_dp.dp_bc
 727 #define pz_mod          pz_dp.dp_mod
 728 #define pz_layers       pz_dp.dp_layers
 729         struct iomod *pz_hpa;   /* HPA base address of device */
 730         void *  pz_spa;         /* SPA base address (zero if no SPA exists) */
 731         iodcio_t pz_iodc_io;    /* entry point of device's driver routines */
 732         short   pz_resv;        /* (reserved) */
 733         u_short pz_class;       /* (see below) */
 734 } pz_device_t;
 735
 736 /* pz_class */
 737 #define PCL_NULL        0       /* illegal */
 738 #define PCL_RANDOM      1       /* random access (disk) */
 739 #define PCL_SEQU        2       /* sequential access (tape) */
 740 #define PCL_DUPLEX      7       /* full-duplex point-to-point (RS-232, Net) */
 741 #define PCL_KEYBD       8       /* half-duplex input (HIL Keyboard) */
 742 #define PCL_DISPL       9       /* half-duplex ouptput (display) */
 743 #define PCL_FC          10      /* fibre channel access media */
 744 #define PCL_CLASS_MASK  0xf     /* XXX class mask */
 745 #define PCL_NET_MASK    0x1000  /* mask for bootp/tftp device */
 746
 747 /*
 748  * The following structure defines what a particular IODC returns when
 749  * given the IODC_DATA argument.
 750  */
 751 struct iodc_data {
 752         u_int   iodc_model: 8,          /* hardware model number */
 753                 iodc_revision:8,        /* software revision */
 754                 iodc_spa_io: 1,         /* 0:memory, 1:device */
 755                 iodc_spa_pack:1,        /* 1:packed multiplexor */
 756                 iodc_spa_enb:1,         /* 1:has an spa */
 757                 iodc_spa_shift:5,       /* power of two # bytes in SPA space */
 758                 iodc_more: 1,           /* iodc_data is: 0:8-byte, 1:16-byte */
 759                 iodc_word: 1,           /* iodc_data is: 0:byte, 1:word */
 760                 iodc_pf: 1,             /* 1:supports powerfail */
 761                 iodc_type: 5;           /* see below */
 762         u_int   iodc_sv_rev: 4,         /* software version revision number */
 763                 iodc_sv_model:20,       /* software interface model # */
 764                 iodc_sv_opt: 8;         /* type-specific options */
 765         u_char  iodc_rev;               /* revision number of IODC code */
 766         u_char  iodc_dep;               /* module-dependent information */
 767         u_char  iodc_rsv[2];            /* reserved */
 768         u_short iodc_cksum;             /* 16-bit checksum of whole IODC */
 769         u_short iodc_length;            /* number of entry points in IODC */
 770                 /* IODC entry points follow... */
 771 };
 772
 773 extern pdcio_t pdc;
 774
 775 #ifdef _KERNEL
 776 struct consdev;
 777
 778 extern int kernelmapped;
 779
 780 void pdc_init(void);
 781 int pdc_call(iodcio_t, int, ...);
 782
 783 void pdccnprobe(struct consdev *);
 784 void pdccninit(struct consdev *);
 785 int pdccngetc(dev_t);
 786 void pdccnputc(dev_t, int);
 787 void pdccnpollc(dev_t, int);
 788 #endif
 789
 790 #endif  /* !(_LOCORE) */
 791
 792 #endif  /* _MACHINE_PDC_H_ */