sys/arch/hpcmips/dev/plumpcmciareg.h

   1 /*      $NetBSD: plumpcmciareg.h,v 1.4 2001/09/15 12:47:07 uch Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /* (CS3) */
  33 #define PLUM_PCMCIA_REGBASE             0x5000
  34 #define PLUM_PCMCIA_REGSIZE             0x1000
  35
  36 /* (MCS0) */
  37 /* 1MByte */
  38 #define PLUM_PCMCIA_IOBASE1             0x00600000
  39 #define PLUM_PCMCIA_IOSIZE1             0x00100000
  40 /* 1MByte */
  41 #define PLUM_PCMCIA_IOBASE2             0x00700000
  42 #define PLUM_PCMCIA_IOSIZE2             0x00100000
  43 /* 8Mbyte */
  44 #define PLUM_PCMCIA_MEMBASE1            0x00800000
  45 #define PLUM_PCMCIA_MEMSIZE1            0x00800000
  46 /* 16MByte */
  47 #define PLUM_PCMCIA_MEMBASE2            0x01000000
  48 #define PLUM_PCMCIA_MEMSIZE2            0x01000000
  49 /* 32MByte */
  50 #define PLUM_PCMCIA_MEMBASE3            0x02000000
  51 #define PLUM_PCMCIA_MEMSIZE3            0x02000000
  52  /* (MCS1) */
  53 /* 64MByte */
  54 #define PLUM_PCMCIA_MEMBASE4            0x04000000
  55 #define PLUM_PCMCIA_MEMSIZE4            0x04000000
  56
  57 /*
  58  * # of slots
  59  */
  60 #define PLUMPCMCIA_NSLOTS 2
  61 /*
  62  * Control registers.
  63  */
  64 #define PLUM_PCMCIA_REGSPACE_SLOT0      0
  65 #define PLUM_PCMCIA_REGSPACE_SLOT1      0x800
  66 #define PLUM_PCMCIA_REGSPACE_SIZE       0x800
  67
  68 #define PLUM_PCMCIA_IDENT               0x000
  69 #define PLUM_PCMCIA_STATUS              0x004
  70 #define PLUM_PCMCIA_STATUS_BVD1                         0x01
  71 #define PLUM_PCMCIA_STATUS_BVD2                         0x02
  72 #define PLUM_PCMCIA_STATUS_CD1                          0x04
  73 #define PLUM_PCMCIA_STATUS_CD2                          0x08
  74 #define PLUM_PCMCIA_STATUS_WRITEPROTECT                 0x10
  75 /* really READY/!BUSY */
  76 #define PLUM_PCMCIA_STATUS_READY                        0x20
  77 #define PLUM_PCMCIA_STATUS_PWROK                        0x40
  78
  79 #define PLUM_PCMCIA_PWRCTRL             0x008
  80 /* output enable */
  81 #define PLUM_PCMCIA_PWRCTRL_OE                          0x80
  82 #define PLUM_PCMCIA_PWRCTRL_DISABLE_RESETDRV            0x40
  83 #define PLUM_PCMCIA_PWRCTRL_AUTOSWITCH_ENABLE           0x20
  84 #define PLUM_PCMCIA_PWRCTRL_PWR_ENABLE                  0x10
  85 #define PLUM_PCMCIA_PWRCTRL_VCC_CTRLBIT1                0x08
  86 #define PLUM_PCMCIA_PWRCTRL_VCC_CTRLBIT0                0x04
  87 #define PLUM_PCMCIA_PWRCTRL_VPP1_CTRLBIT1               0x02
  88 #define PLUM_PCMCIA_PWRCTRL_VPP1_CTRLBIT0               0x01
  89
  90 #define PLUM_PCMCIA_GENCTRL                             0x00c
  91 /* active low (zero) */
  92 #define PLUM_PCMCIA_GENCTRL_RESET                       0x40
  93 #define PLUM_PCMCIA_GENCTRL_CARDTYPE_MASK               0x20
  94 #define PLUM_PCMCIA_GENCTRL_CARDTYPE_IO                 0x20
  95 #define PLUM_PCMCIA_GENCTRL_CARDTYPE_MEM                0x00
  96
  97 #define PLUM_PCMCIA_CSCINT_STAT                         0x010
  98 #define PLUM_PCMCIA_CSCINT                              0x014
  99 #define PLUM_PCMCIA_CSCINT_BATTERY_DEAD                 0x01
 100 #define PLUM_PCMCIA_CSCINT_BATTERY_WARNING              0x02
 101 #define PLUM_PCMCIA_CSCINT_READY                        0x04
 102 #define PLUM_PCMCIA_CSCINT_CARD_DETECT                  0x08
 103
 104 #define PLUM_PCMCIA_WINEN                               0x018
 105 #define PLUM_PCMCIA_WINEN_IO1                           0x00000080
 106 #define PLUM_PCMCIA_WINEN_IO0                           0x00000040
 107 #define PLUM_PCMCIA_WINEN_MEM4                          0x00000010
 108 #define PLUM_PCMCIA_WINEN_MEM3                          0x00000008
 109 #define PLUM_PCMCIA_WINEN_MEM2                          0x00000004
 110 #define PLUM_PCMCIA_WINEN_MEM1                          0x00000002
 111 #define PLUM_PCMCIA_WINEN_MEM0                          0x00000001
 112 #define PLUM_PCMCIA_WINEN_MEM(x)        (1 << (x))
 113
 114 #define PLUM_PCMCIA_MEM_WINS                            5
 115 #define PLUM_PCMCIA_MEM_SHIFT                           12
 116 #define PLUM_PCMCIA_MEM_PAGESIZE                (1<<PLUM_PCMCIA_MEM_SHIFT)
 117
 118 #define PLUM_PCMCIA_IO_WINS                             2
 119
 120 #define PLUM_PCMCIA_IOWINCTRL                           0x01c
 121 #define PLUM_PCMCIA_IOWINCTRL_WINMASK                   0x0000000f
 122 #define PLUM_PCMCIA_IOWINCTRL_WIN0SHIFT                 0
 123 #define PLUM_PCMCIA_IOWINCTRL_WIN1SHIFT                 4
 124 #define PLUM_PCMCIA_IOWINCTRL_DATASIZE16                0x00000001
 125 #define PLUM_PCMCIA_IOWINCTRL_IOCS16SRC                 0x00000002
 126 #define PLUM_PCMCIA_IOWINCTRL_ZEROWAIT                  0x00000004
 127 #define PLUM_PCMCIA_IOWINCTRL_WAITSTATE                 0x00000008
 128
 129 #define PLUM_PCMCIA_IOWIN0STARTADDR     0x020
 130 #define PLUM_PCMCIA_IOWIN1STARTADDR     0x030
 131 #define PLUM_PCMCIA_IOWINSTARTADDR(x)                                   \
 132         ((x) * 0x10 + PLUM_PCMCIA_IOWIN0STARTADDR)
 133
 134 #define PLUM_PCMCIA_IOWIN0STOPADDR      0x024
 135 #define PLUM_PCMCIA_IOWIN1STOPADDR      0x034
 136 #define PLUM_PCMCIA_IOWINSTOPADDR(x)                                    \
 137         ((x) * 0x10 + PLUM_PCMCIA_IOWIN0STOPADDR)
 138
 139 #define PLUM_PCMCIA_IOWIN0ADDRCTRL      0x028
 140 #define PLUM_PCMCIA_IOWIN1ADDRCTRL      0x038
 141 #define PLUM_PCMCIA_IOWINADDRCTRL(x)                                    \
 142         ((x) * 0x10 + PLUM_PCMCIA_IOWIN0ADDRCTRL)
 143
 144 #define PLUM_PCMCIA_IOWINADDRCTRL_AREA1 0x00000000
 145 #define PLUM_PCMCIA_IOWINADDRCTRL_AREA2 0x00000001
 146
 147 #define PLUM_PCMCIA_MEMWIN0STARTADDR    0x040
 148 #define PLUM_PCMCIA_MEMWIN1STARTADDR    0x060
 149 #define PLUM_PCMCIA_MEMWIN2STARTADDR    0x080
 150 #define PLUM_PCMCIA_MEMWIN3STARTADDR    0x0a0
 151 #define PLUM_PCMCIA_MEMWIN4STARTADDR    0x0c0
 152 #define PLUM_PCMCIA_MEMWINSTARTADDR(x)                                  \
 153         ((x) * 0x20 + PLUM_PCMCIA_MEMWIN0STARTADDR)
 154
 155 #define PLUM_PCMCIA_MEMWIN0STOPADDR     0x044
 156 #define PLUM_PCMCIA_MEMWIN1STOPADDR     0x064
 157 #define PLUM_PCMCIA_MEMWIN2STOPADDR     0x084
 158 #define PLUM_PCMCIA_MEMWIN3STOPADDR     0x0a4
 159 #define PLUM_PCMCIA_MEMWIN4STOPADDR     0x0c4
 160 #define PLUM_PCMCIA_MEMWINSTOPADDR(x)                                   \
 161         ((x) * 0x20 + PLUM_PCMCIA_MEMWIN0STOPADDR)
 162
 163 #define PLUM_PCMCIA_MEMWIN0OFSADDR      0x048
 164 #define PLUM_PCMCIA_MEMWIN1OFSADDR      0x068
 165 #define PLUM_PCMCIA_MEMWIN2OFSADDR      0x088
 166 #define PLUM_PCMCIA_MEMWIN3OFSADDR      0x0a8
 167 #define PLUM_PCMCIA_MEMWIN4OFSADDR      0x0c8
 168 #define PLUM_PCMCIA_MEMWINOFSADDR(x)                                    \
 169         ((x) * 0x20 + PLUM_PCMCIA_MEMWIN0OFSADDR)
 170
 171 #define PLUM_PCMCIA_MEMWIN0CTRL         0x04c
 172 #define PLUM_PCMCIA_MEMWIN1CTRL         0x06c
 173 #define PLUM_PCMCIA_MEMWIN2CTRL         0x08c
 174 #define PLUM_PCMCIA_MEMWIN3CTRL         0x0ac
 175 #define PLUM_PCMCIA_MEMWIN4CTRL         0x0cc
 176 #define PLUM_PCMCIA_MEMWINCTRL(x)                                       \
 177         ((x) * 0x20 + PLUM_PCMCIA_MEMWIN0CTRL)
 178
 179 #define PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT        24
 180 #define PLUM_PCMCIA_MEMWINCTRL_MAP_MASK         0x3
 181 #define PLUM_PCMCIA_MEMWINCTRL_MAP(cr)                                  \
 182         (((cr) >> PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT) &                   \
 183         PLUM_PCMCIA_MEMWINCTRL_MAP_MASK)
 184 #define PLUM_PCMCIA_MEMWINCTRL_MAP_SET(cr, val)                         \
 185         ((cr) | (((val) << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT) &          \
 186         (PLUM_PCMCIA_MEMWINCTRL_MAP_MASK << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT)))
 187 #define PLUM_PCMCIA_MEMWINCTRL_MAP_CLEAR(cr)                            \
 188         ((cr) &= ~(PLUM_PCMCIA_MEMWINCTRL_MAP_MASK << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT))
 189 #define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA1        0x0
 190 #define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA2        0x1
 191 #define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA3        0x2
 192 #define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA4        0x3
 193
 194 #define PLUM_PCMCIA_MEMWINCTRL_WRPROTECT        0x00800000
 195 #define PLUM_PCMCIA_MEMWINCTRL_REGACTIVE        0x00400000
 196 #define PLUM_PCMCIA_MEMWINCTRL_DATASIZE16       0x00000080
 197 #define PLUM_PCMCIA_MEMWINCTRL_ZERO_WS          0x00000040
 198
 199 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT     14
 200 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK      0x3
 201 #define PLUM_PCMCIA_MEMWINCTRL_TIMING(cr)                               \
 202         (((cr) >> PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT) &                \
 203         PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK)
 204 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_SET(cr, val)                      \
 205         ((cr) | (((val) << PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT) &       \
 206         (PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK <<                          \
 207         PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT)))
 208 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_STD       0x0
 209 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_1WAIT     0x1
 210 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_2WAIT     0x2
 211 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_3WAIT     0x3
 212
 213 #define PLUM_PCMCIA_MEMWINCTRL_DATASIZE_16BIT   0x00000080 /* else 8bit */
 214 #define PLUM_PCMCIA_MEMWINCTRL_ZEROWS           0x00000040
 215
 216 #define PLUM_PCMCIA_GENCTRL2            0x058
 217 #define PLUM_PCMCIA_GENCTRL2_VCC5V      0x000000c0
 218 #define PLUM_PCMCIA_GENCTRL2_VCC3V      0x00000080
 219
 220 #define PLUM_PCMCIA_GLOBALCTRL          0x078
 221 #define PLUM_PCMCIA_GLOBALCTRL_EXPLICIT_WB_CSC_INT      0x04
 222
 223 #define PLUM_PCMCIA_TIMING              0x0ec
 224
 225 #define PLUM_PCMCIA_FUNCCTRL            0x0f8
 226 #define PLUM_PCMCIA_FUNCCTRL_3VSUPPORT  0x00000001
 227 #define PLUM_PCMCIA_FUNCCTRL_VSSEN      0x00000002
 228
 229 #define PLUM_PCMCIA_SPECIALMODE         0x0fc
 230
 231 #define PLUM_PCMCIA_SLOTCTRL            0x100
 232 #define PLUM_PCMCIA_SLOTCTRL_ENABLE     0x00000080
 233
 234 #define PLUM_PCMCIA_BUFOFF              0x104
 235 #define PLUM_PCMCIA_CARDDETECTMODE      0x108
 236 #define PLUM_PCMCIA_CARDPWRCTRL         0x10c
 237 #define PLUM_PCMCIA_CARDPWRCTRL_OFF     1
 238 #define PLUM_PCMCIA_CARDPWRCTRL_ON      0