1 /* $NetBSD: bcureg.h,v 1.8 2001/09/05 16:08:46 sato Exp $ */
4 * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
5 * Copyright (c) 1999 PocketBSD Project. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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17 * This product includes software developed by the PocketBSD project
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32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * BCU (Bus Control Unit) Registers definitions.
39 * start 0xB000000 (vr4101,4102,4111,4121)
40 * start 0xA000000 (vr4181)
41 * start 0xF000000 (vr4122, vr4131)
44 #define BCUCNT1_REG_W 0x000 /* BCU Control Register 1 */
46 #define BCUCNT1_ROMMASK (1<<15) /* ROM SIZE (<= 4121,>= 4102) */
47 #define BCUCNT1_ROM64M (1<<15) /* ROM SIZE 64Mbit*/
48 #define BCUCNT1_ROM32M (0<<15) /* ROM SIZE 32Mbit*/
50 #define BCUCNT1_DRAMMASK (1<<14) /* DRAM SIZE (<= 4121,>= 4102) */
51 #define BCUCNT1_DRAM64M (1<<14) /* DRAM SIZE 64Mbit*/
52 #define BCUCNT1_DRAM32M (0<<14) /* DRAM SIZE 32Mbit*/
54 #define BCUCNT1_ROMSMASK (0x3<<14) /* ROM SIZE (=4181) */
55 #define BCUCNT1_ROMS64M (0x2<<14) /* ROM SIZE 64Mbit */
56 #define BCUCNT1_ROMS32M (0x1<<14) /* ROM SIZE 32Mbit */
58 #define BCUCNT1_ISAMLCD (1<<13) /* ISAM/LCD 0x0a000000 to 0xaffffff(>= 4102) */
59 #define BCUCNT1_ISA (1<<13) /* ISA memory space */
60 #define BCUCNT1_LCD (0<<13) /* LCD space*/
62 #define BCUCNT1_PAGEMASK (1<<12) /* Maximum burst access size for Page Rom (<= 4121,>= 4102) */
63 #define BCUCNT1_PAGE128 (1<<12) /* 128bit */
64 #define BCUCNT1_PAGE64 (0<<12) /* 64bit */
66 #define BCUCNT1_PAGESIZEMASK (3<<12) /* PageROM PAGESIZE (= 4122, 4131) */
67 #define BCUCNT1_PASESIZE32 (2<<12) /* 32 byte */
68 #define BCUCNT1_PASESIZE16 (1<<12) /* 16 byte */
69 #define BCUCNT1_PASESIZE8 (0<<12) /* 8 byte */
71 #define BCUCNT1_PAGE2MASK (1<<10) /* (<= 4131,>= 4102) */
72 #define BCUCNT1_PAGE2PAGE (1<<10) /* Page ROM */
73 #define BCUCNT1_PAGE2ORD (0<<10) /* Prginary ROM */
75 #define BCUCNT1_PAGE0MASK (1<<8) /* (<= 4131,>= 4102) */
76 #define BCUCNT1_PAGE0PAGE (1<<8) /* Page ROM */
77 #define BCUCNT1_PAGE0ORD (0<<8) /* Prginary ROM */
79 #define BCUCNT1_REFMASK (1<<7) /* DRAM refresh interval (= 4101) */
80 #define BCUCNT1_REF1024 (1<<7) /* 1024 cycles/128ms */
81 #define BCUCNT1_REF4096 (0<<7) /* 4096 cycles/128ms */
83 #define BCUCNT1_ROMWEN2 (1<<6) /* Enable Flash memory write ROM 2 (<= 4131,>= 4102) */
84 #define BCUCNT1_ROMWEN2EN (1<<6) /* Enable */
85 #define BCUCNT1_ROMWEN2DS (0<<6) /* Prohibit */
87 #define BCUCNT1_PAGEROM (1<<6) /* Enable page ROM access (= 4101) */
88 #define BCUCNT1_PAGEROMEN (1<<6) /* Page ROM */
89 #define BCUCNT1_PAGEROMDIS (0<<6) /* not Page ROM */
91 #define BCUCNT1_ROMWEN (1<<5) /* Enable Flash memory write ROM 0 (= 4101) */
92 #define BCUCNT1_ROMWENEN (1<<5) /* Enable */
93 #define BCUCNT1_ROMWENDS (0<<5) /* Prohibit */
95 #define BCUCNT1_ROMWEN0 (1<<4) /* Enable Flash memory write ROM 0 (<= 4131,>= 4102, =4181) */
96 #define BCUCNT1_ROMWEN0EN (1<<4) /* Enable */
97 #define BCUCNT1_ROMWEN0DS (0<<4) /* Prohibit */
99 #define BCUCNT1_SRFSTAT (1<<4) /* DRAM refresh mode (= 4101) */
100 #define BCUCNT1_SRFSTATSRF (1<<4) /* self refresh */
101 #define BCUCNT1_SRFSTATCBR (0<<4) /* CBR refresh */
103 #define BCUCNT1_BCPUR (1<<3) /* CPU bus cycle control (= 4101) */
104 #define BCUCNT1_BCPUREN (1<<3) /* CPU bus cycle control enable */
105 #define BCUCNT1_BCPURDIS (0<<3) /* CPU bus cycle control disable */
107 #define BCUCNT1_HLD (1<<2) /* Bus hold enable (= 4122, 4131) */
108 #define BCUCNT1_HLDEN (1<<2) /* enable */
109 #define BCUCNT1_HLDDIS (1<<2) /* disable */
111 #define BCUCNT1_BUSHERR (1<<1) /* Bus Timeout detection enable (<= 4121,>= 4102) */
113 #define BCUCNT1_BUSHERREN (1<<1) /* Enable */
114 #define BCUCNT1_BUSHERRDS (0<<1) /* Prohibit */
116 #define BCUCNT1_RTYPE (0x3<<1) /* ROM type (=4181) */
117 #define BCUCNT1_RTOROM (0<<1) /* Odinary ROM */
118 #define BCUCNT1_RTFLASH (1<<1) /* flash ROM */
119 #define BCUCNT1_RTPAGEROM (2<<1) /* Page ROM */
121 #define BCUCNT1_RSTOUT (1) /* RSTOUT control bit */
122 #define BCUCNT1_RSTOUTH (1) /* RSTOUT high level*/
123 #define BCUCNT1_RSTOUTL (0) /* RSTOUT low level*/
126 #define BCUCNT2_REG_W 0x002 /* BCU Control Register 2 (<= 4121,>= 4102, =4181) */
128 #define BCUCNT2_GMODE (1) /* LCD access control */
129 #define BCUCNT2_GMODENOM (1) /* not invert LCD */
130 #define BCUCNT2_GMODEINV (0) /* invert LCD */
132 #define BCUBR_REG_W 0x002 /* BCU Bus Restrain Register (= 4101) */
134 #define BCUROMSIZE_REG_W 0x004 /* ROM size setting register (= 4122, 4131) */
135 #define BCUROMSIZE_SIZE3 (7<<12) /* Bank3 size */
136 #define BCUROMSIZE_SIZE3_64 (5<<12) /* 64MB */
137 #define BCUROMSIZE_SIZE3_32 (4<<12) /* 32MB */
138 #define BCUROMSIZE_SIZE3_16 (3<<12) /* 16MB */
139 #define BCUROMSIZE_SIZE3_8 (2<<12) /* 8MB */
140 #define BCUROMSIZE_SIZE3_4 (1<<12) /* 4MB */
142 #define BCUROMSIZE_SIZE2 (7<<8) /* Bank2 size */
143 #define BCUROMSIZE_SIZE2_64 (5<<8) /* 64MB */
144 #define BCUROMSIZE_SIZE2_32 (4<<8) /* 32MB */
145 #define BCUROMSIZE_SIZE2_16 (3<<8) /* 16MB */
146 #define BCUROMSIZE_SIZE2_8 (2<<8) /* 8MB */
147 #define BCUROMSIZE_SIZE2_4 (1<<8) /* 4MB */
149 #define BCUROMSIZE_SIZE1 (7<<4) /* Bank1 size */
150 #define BCUROMSIZE_SIZE1_64 (5<<4) /* 64MB */
151 #define BCUROMSIZE_SIZE1_32 (4<<4) /* 32MB */
152 #define BCUROMSIZE_SIZE1_16 (3<<4) /* 16MB */
153 #define BCUROMSIZE_SIZE1_8 (2<<4) /* 8MB */
154 #define BCUROMSIZE_SIZE1_4 (1<<4) /* 4MB */
156 #define BCUROMSIZE_SIZE0 (7) /* Bank0 size */
157 #define BCUROMSIZE_SIZE0_64 (5) /* 64MB */
158 #define BCUROMSIZE_SIZE0_32 (4) /* 32MB */
159 #define BCUROMSIZE_SIZE0_16 (3) /* 16MB */
160 #define BCUROMSIZE_SIZE0_8 (2) /* 8MB */
161 #define BCUROMSIZE_SIZE0_4 (1) /* 4MB */
163 #define BCUBRCNT_REG_W 0x004 /* BCU Bus Restrain Count Register (= 4101) */
165 #define BCUROMSPEED_REG_W 0x006 /* BCU ROM Speed Register (=4122, 4131) */
166 #define BCUROMSPEED_PATIME (0x3<<12) /* Page Access time */
167 #define BCUROMSPEED_PATIME_5VT (0x3<<12) /* 5VTClock */
168 #define BCUROMSPEED_PATIME_4VT (0x2<<12) /* 4VTClock */
169 #define BCUROMSPEED_PATIME_3VT (0x1<<12) /* 3VTClock */
170 #define BCUROMSPEED_PATIME_2VT (0x0<<12) /* 2VTClock */
172 #define BCUROMSPEED_ATIME (0xf) /* Access time */
173 #define BCUROMSPEED_ATIME_18VT (0xf) /* 18VTClock */
174 #define BCUROMSPEED_ATIME_17VT (0xe) /* 17VTClock */
175 #define BCUROMSPEED_ATIME_16VT (0xd) /* 16VTClock */
176 #define BCUROMSPEED_ATIME_15VT (0xc) /* 15VTClock */
177 #define BCUROMSPEED_ATIME_14VT (0xb) /* 14VTClock */
178 #define BCUROMSPEED_ATIME_13VT (0xa) /* 13VTClock */
179 #define BCUROMSPEED_ATIME_12VT (0x9) /* 12VTClock */
180 #define BCUROMSPEED_ATIME_11VT (0x8) /* 11VTClock */
181 #define BCUROMSPEED_ATIME_10VT (0x7) /* 10VTClock */
182 #define BCUROMSPEED_ATIME_9VT (0x6) /* 9VTClock */
183 #define BCUROMSPEED_ATIME_8VT (0x5) /* 8VTClock */
184 #define BCUROMSPEED_ATIME_7VT (0x4) /* 7VTClock */
185 #define BCUROMSPEED_ATIME_6VT (0x3) /* 6VTClock */
186 #define BCUROMSPEED_ATIME_5VT (0x2) /* 5VTClock */
187 #define BCUROMSPEED_ATIME_4VT (0x1) /* 4VTClock */
188 #define BCUROMSPEED_ATIME_3VT (0x0) /* 3VTClock */
190 #define BCUBCL_REG_W 0x006 /* BCU CPU Restrain Disable Register (= 4101) */
192 #define BCUIO0SPEED_REG_W 0x008 /* BCU IO0 Speed Register (=4122, 4131) */
193 #define BCUIO0SPEED_RWCS (0x3<<12) /* R/W - CS time */
194 #define BCUIO0SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */
195 #define BCUIO0SPEED_RWCS_4VT (0x2<<12) /* 4VTClock */
196 #define BCUIO0SPEED_RWCS_3VT (0x1<<12) /* 3VTClock */
197 #define BCUIO0SPEED_RWCS_2VT (0x0<<12) /* 2VTClock */
199 #define BCUIO0SPEED_RDYRW (0xf<<8) /* IORDY-R/W time */
200 #define BCUIO0SPEED_RDYRW_18VT (0xf) /* 18VTClock */
201 #define BCUIO0SPEED_RDYRW_17VT (0xe) /* 17VTClock */
202 #define BCUIO0SPEED_RDYRW_16VT (0xd) /* 16VTClock */
203 #define BCUIO0SPEED_RDYRW_15VT (0xc) /* 15VTClock */
204 #define BCUIO0SPEED_RDYRW_14VT (0xb) /* 14VTClock */
205 #define BCUIO0SPEED_RDYRW_13VT (0xa) /* 13VTClock */
206 #define BCUIO0SPEED_RDYRW_12VT (0x9) /* 12VTClock */
207 #define BCUIO0SPEED_RDYRW_11VT (0x8) /* 11VTClock */
208 #define BCUIO0SPEED_RDYRW_10VT (0x7) /* 10VTClock */
209 #define BCUIO0SPEED_RDYRW_9VT (0x6) /* 9VTClock */
210 #define BCUIO0SPEED_RDYRW_8VT (0x5) /* 8VTClock */
211 #define BCUIO0SPEED_RDYRW_7VT (0x4) /* 7VTClock */
212 #define BCUIO0SPEED_RDYRW_6VT (0x3) /* 6VTClock */
213 #define BCUIO0SPEED_RDYRW_5VT (0x2) /* 5VTClock */
214 #define BCUIO0SPEED_RDYRW_4VT (0x1) /* 4VTClock */
215 #define BCUIO0SPEED_RDYRW_3VT (0x0) /* 3VTClock */
217 #define BCUIO0SPEED_RWRDY (0xf<<4) /* R/W-IORDY time */
218 #define BCUIO0SPEED_RWRDY_14VT (0xf) /* 14VTClock */
219 #define BCUIO0SPEED_RWRDY_13VT (0xe) /* 13VTClock */
220 #define BCUIO0SPEED_RWRDY_12VT (0xd) /* 12VTClock */
221 #define BCUIO0SPEED_RWRDY_11VT (0xc) /* 11VTClock */
222 #define BCUIO0SPEED_RWRDY_10VT (0xb) /* 10VTClock */
223 #define BCUIO0SPEED_RWRDY_9VT (0xa) /* 9VTClock */
224 #define BCUIO0SPEED_RWRDY_8VT (0x9) /* 8VTClock */
225 #define BCUIO0SPEED_RWRDY_7VT (0x8) /* 7VTClock */
226 #define BCUIO0SPEED_RWRDY_6VT (0x7) /* 6VTClock */
227 #define BCUIO0SPEED_RWRDY_5VT (0x6) /* 5VTClock */
228 #define BCUIO0SPEED_RWRDY_4VT (0x5) /* 4VTClock */
229 #define BCUIO0SPEED_RWRDY_3VT (0x4) /* 3VTClock */
230 #define BCUIO0SPEED_RWRDY_2VT (0x3) /* 2VTClock */
231 #define BCUIO0SPEED_RWRDY_1VT (0x2) /* 1VTClock */
232 #define BCUIO0SPEED_RWRDY_0VT (0x1) /* 0VTClock */
233 #define BCUIO0SPEED_RWRDY_M1VT (0x0) /* -1VTClock */
235 #define BCUIO0SPEED_CSRW (0xf<<0) /* IORDY-R/W time */
236 #define BCUIO0SPEED_CSRW_16VT (0xf) /* 16VTClock */
237 #define BCUIO0SPEED_CSRW_15VT (0xe) /* 15VTClock */
238 #define BCUIO0SPEED_CSRW_14VT (0xd) /* 14VTClock */
239 #define BCUIO0SPEED_CSRW_13VT (0xc) /* 13VTClock */
240 #define BCUIO0SPEED_CSRW_12VT (0xb) /* 12VTClock */
241 #define BCUIO0SPEED_CSRW_11VT (0xa) /* 11VTClock */
242 #define BCUIO0SPEED_CSRW_10VT (0x9) /* 10VTClock */
243 #define BCUIO0SPEED_CSRW_9VT (0x8) /* 9VTClock */
244 #define BCUIO0SPEED_CSRW_8VT (0x7) /* 8VTClock */
245 #define BCUIO0SPEED_CSRW_7VT (0x6) /* 7VTClock */
246 #define BCUIO0SPEED_CSRW_6VT (0x5) /* 6VTClock */
247 #define BCUIO0SPEED_CSRW_5VT (0x4) /* 5VTClock */
248 #define BCUIO0SPEED_CSRW_4VT (0x3) /* 4VTClock */
249 #define BCUIO0SPEED_CSRW_3VT (0x2) /* 3VTClock */
250 #define BCUIO0SPEED_CSRW_2VT (0x1) /* 2VTClock */
251 #define BCUIO0SPEED_CSRW_1VT (0x0) /* 1VTClock */
253 #define BCUBCLCNT_REG_W 0x008 /* BCU CPU Restrain Disable Count Register (= 4101) */
255 #define BCUIO1SPEED_REG_W 0x00A /* BCU IO1 Speed Register (=4122, 4131) */
256 #define BCUIO1SPEED_RWCS (0x3<<12) /* R/W - CS time */
257 #define BCUIO1SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */
258 #define BCUIO1SPEED_RWCS_4VT (0x2<<12) /* 4VTClock */
259 #define BCUIO1SPEED_RWCS_3VT (0x1<<12) /* 3VTClock */
260 #define BCUIO1SPEED_RWCS_2VT (0x0<<12) /* 2VTClock */
262 #define BCUIO1SPEED_RDYRW (0xf<<8) /* IORDY-R/W time */
263 #define BCUIO1SPEED_RDYRW_18VT (0xf) /* 18VTClock */
264 #define BCUIO1SPEED_RDYRW_17VT (0xe) /* 17VTClock */
265 #define BCUIO1SPEED_RDYRW_16VT (0xd) /* 16VTClock */
266 #define BCUIO1SPEED_RDYRW_15VT (0xc) /* 15VTClock */
267 #define BCUIO1SPEED_RDYRW_14VT (0xb) /* 14VTClock */
268 #define BCUIO1SPEED_RDYRW_13VT (0xa) /* 13VTClock */
269 #define BCUIO1SPEED_RDYRW_12VT (0x9) /* 12VTClock */
270 #define BCUIO1SPEED_RDYRW_11VT (0x8) /* 11VTClock */
271 #define BCUIO1SPEED_RDYRW_10VT (0x7) /* 10VTClock */
272 #define BCUIO1SPEED_RDYRW_9VT (0x6) /* 9VTClock */
273 #define BCUIO1SPEED_RDYRW_8VT (0x5) /* 8VTClock */
274 #define BCUIO1SPEED_RDYRW_7VT (0x4) /* 7VTClock */
275 #define BCUIO1SPEED_RDYRW_6VT (0x3) /* 6VTClock */
276 #define BCUIO1SPEED_RDYRW_5VT (0x2) /* 5VTClock */
277 #define BCUIO1SPEED_RDYRW_4VT (0x1) /* 4VTClock */
278 #define BCUIO1SPEED_RDYRW_3VT (0x0) /* 3VTClock */
280 #define BCUIO1SPEED_RWRDY (0xf<<4) /* R/W-IORDY time */
281 #define BCUIO1SPEED_RWRDY_14VT (0xf) /* 14VTClock */
282 #define BCUIO1SPEED_RWRDY_13VT (0xe) /* 13VTClock */
283 #define BCUIO1SPEED_RWRDY_12VT (0xd) /* 12VTClock */
284 #define BCUIO1SPEED_RWRDY_11VT (0xc) /* 11VTClock */
285 #define BCUIO1SPEED_RWRDY_10VT (0xb) /* 10VTClock */
286 #define BCUIO1SPEED_RWRDY_9VT (0xa) /* 9VTClock */
287 #define BCUIO1SPEED_RWRDY_8VT (0x9) /* 8VTClock */
288 #define BCUIO1SPEED_RWRDY_7VT (0x8) /* 7VTClock */
289 #define BCUIO1SPEED_RWRDY_6VT (0x7) /* 6VTClock */
290 #define BCUIO1SPEED_RWRDY_5VT (0x6) /* 5VTClock */
291 #define BCUIO1SPEED_RWRDY_4VT (0x5) /* 4VTClock */
292 #define BCUIO1SPEED_RWRDY_3VT (0x4) /* 3VTClock */
293 #define BCUIO1SPEED_RWRDY_2VT (0x3) /* 2VTClock */
294 #define BCUIO1SPEED_RWRDY_1VT (0x2) /* 1VTClock */
295 #define BCUIO1SPEED_RWRDY_0VT (0x1) /* 0VTClock */
296 #define BCUIO1SPEED_RWRDY_M1VT (0x0) /* -1VTClock */
298 #define BCUIO1SPEED_CSRW (0xf<<0) /* IORDY-R/W time */
299 #define BCUIO1SPEED_CSRW_16VT (0xf) /* 16VTClock */
300 #define BCUIO1SPEED_CSRW_15VT (0xe) /* 15VTClock */
301 #define BCUIO1SPEED_CSRW_14VT (0xd) /* 14VTClock */
302 #define BCUIO1SPEED_CSRW_13VT (0xc) /* 13VTClock */
303 #define BCUIO1SPEED_CSRW_12VT (0xb) /* 12VTClock */
304 #define BCUIO1SPEED_CSRW_11VT (0xa) /* 11VTClock */
305 #define BCUIO1SPEED_CSRW_10VT (0x9) /* 10VTClock */
306 #define BCUIO1SPEED_CSRW_9VT (0x8) /* 9VTClock */
307 #define BCUIO1SPEED_CSRW_8VT (0x7) /* 8VTClock */
308 #define BCUIO1SPEED_CSRW_7VT (0x6) /* 7VTClock */
309 #define BCUIO1SPEED_CSRW_6VT (0x5) /* 6VTClock */
310 #define BCUIO1SPEED_CSRW_5VT (0x4) /* 5VTClock */
311 #define BCUIO1SPEED_CSRW_4VT (0x3) /* 4VTClock */
312 #define BCUIO1SPEED_CSRW_3VT (0x2) /* 3VTClock */
313 #define BCUIO1SPEED_CSRW_2VT (0x1) /* 2VTClock */
314 #define BCUIO1SPEED_CSRW_1VT (0x0) /* 1VTClock */
316 #define BCUSPEED_REG_W 0x00A /* BCU Access Cycle Change Register (4121>=4102)*/
318 #define BCUSPD_WPROM (0x3<<12) /* Page ROM access speed */
319 #define BCUSPD_WPROMRFU (0x3<<12) /* RFU */
320 #define BCUSPD_WPROM1T (0x2<<12) /* 1TClock */
321 #define BCUSPD_WPROM2T (0x1<<12) /* 2TClock */
322 #define BCUSPD_WPROM3T (0x0<<12) /* 3TClock */
324 #define BCUSPD_WLCDM (0x7<<8) /* access speed 0x0a000000-0affffff */
326 /* BCUCNT1_ISAMLCD == BCUCNT1_LCD */
327 #define BCUSPD_WLCDRFU (0x7<<8) /* LCD RFU */
328 #define BCUSPD_WLCDRFU1 (0x6<<8) /* LCD RFU */
329 #define BCUSPD_WLCDRFU2 (0x5<<8) /* LCD RFU */
330 #define BCUSPD_WLCDRFU3 (0x4<<8) /* LCD RFU */
331 #define BCUSPD_WLCD2T (0x3<<8) /* LCD 2TClock */
332 #define BCUSPD_WLCD4T (0x2<<8) /* LCD 4TClock */
333 #define BCUSPD_WLCD6T (0x1<<8) /* LCD 6TClock */
334 #define BCUSPD_WLCD8T (0x0<<8) /* LCD 8TClock */
335 /* BCUCNT1_ISAMLCD == BCUCNT1_ISAM */
336 #define BCUSPD_ISAM1T (0x7<<8) /* ISAM 1TClock */
337 #define BCUSPD_ISAM2T (0x6<<8) /* ISAM 2TClock */
338 #define BCUSPD_ISAM3T (0x5<<8) /* ISAM 3TClock */
339 #define BCUSPD_ISAM4T (0x4<<8) /* ISAM 4TClock */
340 #define BCUSPD_ISAM5T (0x3<<8) /* ISAM 5TClock */
341 #define BCUSPD_ISAM6T (0x2<<8) /* ISAM 6TClock */
342 #define BCUSPD_ISAM7T (0x1<<8) /* ISAM 7TClock */
343 #define BCUSPD_ISAM8T (0x0<<8) /* ISAM 8TClock */
345 #define BCUSPD_WISAA (0x7<<4) /* System Bus Access Speed */
346 #define BCUSPD_WISAA3T (0x5<<4) /* 3TClock */
347 #define BCUSPD_WISAA4T (0x4<<4) /* 4TClock */
348 #define BCUSPD_WISAA5T (0x3<<4) /* 5TClock */
349 #define BCUSPD_WISAA6T (0x2<<4) /* 6TClock */
350 #define BCUSPD_WISAA7T (0x1<<4) /* 7TClock */
351 #define BCUSPD_WISAA8T (0x0<<4) /* 8TClock */
353 #define BCUSPD_WROMA (0x7<<0) /* System Bus Access Speed */
354 #define BCUSPD_WROMA2T (0x7<<0) /* 2TClock */
355 #define BCUSPD_WROMA3T (0x6<<0) /* 3TClock */
356 #define BCUSPD_WROMA4T (0x5<<0) /* 4TClock */
357 #define BCUSPD_WROMA5T (0x4<<0) /* 5TClock */
358 #define BCUSPD_WROMA6T (0x3<<0) /* 6TClock */
359 #define BCUSPD_WROMA7T (0x2<<0) /* 7TClock */
360 #define BCUSPD_WROMA8T (0x1<<0) /* 8TClock */
361 #define BCUSPD_WROMA9T (0x0<<0) /* 9TClock */
364 #define BCUERRST_REG_W 0x00C /* BCU BUS ERROR Status Register (4121>=4102)*/
366 #define BCUERRST_BUSERRMASK (1) /* Bus error, clear to 0 when 1 is written */
367 #define BCUERRST_BUSERR (1) /* Bus error */
368 #define BCUERRST_BUSNORM (0) /* Normal */
370 #define BCU81SPEED_REG_W 0x00C /* BCU Access Cycle Change Register (=4181)*/
372 #define BCU81SPD_WPROM (0x7<<12) /* Page ROM access speed */
373 #define BCU81SPD_WPROM8T (0x7<<12) /* 8TClock */
374 #define BCU81SPD_WPROM7T (0x6<<12) /* 7TClock */
375 #define BCU81SPD_WPROM6T (0x5<<12) /* 6TClock */
376 #define BCU81SPD_WPROM5T (0x4<<12) /* 5TClock */
377 #define BCU81SPD_WPROM4T (0x3<<12) /* 4TClock */
378 #define BCU81SPD_WPROM3T (0x2<<12) /* 3TClock */
379 #define BCU81SPD_WPROM2T (0x1<<12) /* 2TClock */
380 #define BCU81SPD_WPROM1T (0x0<<12) /* 1TClock */
382 #define BCU81SPD_WROMA (0xf<<0) /* System Bus Access Speed */
383 #define BCU81SPD_WROMA16T (0xf<<0) /* 16TClock */
384 #define BCU81SPD_WROMA15T (0xe<<0) /* 15TClock */
385 #define BCU81SPD_WROMA14T (0xd<<0) /* 14TClock */
386 #define BCU81SPD_WROMA13T (0xc<<0) /* 13TClock */
387 #define BCU81SPD_WROMA12T (0xb<<0) /* 12TClock */
388 #define BCU81SPD_WROMA11T (0xa<<0) /* 11TClock */
389 #define BCU81SPD_WROMA10T (0x9<<0) /* 10TClock */
390 #define BCU81SPD_WROMA9T (0x8<<0) /* 9TClock */
391 #define BCU81SPD_WROMA8T (0x7<<0) /* 8TClock */
392 #define BCU81SPD_WROMA7T (0x6<<0) /* 7TClock */
393 #define BCU81SPD_WROMA6T (0x5<<0) /* 6TClock */
394 #define BCU81SPD_WROMA5T (0x4<<0) /* 5TClock */
395 #define BCU81SPD_WROMA4T (0x3<<0) /* 4TClock */
396 #define BCU81SPD_WROMA3T (0x2<<0) /* 3TClock */
397 #define BCU81SPD_WROMA2T (0x1<<0) /* 2TClock */
398 #define BCU81SPD_WROMA1T (0x0<<0) /* 1TClock */
400 #define BCURFCNT_REG_W 0x00E /* BCU Refresh Control Register(4121>=4102) */
401 #define BCU81RFCNT_REG_W 0x010 /* BCU Refresh Control Register(=4181) */
403 #define BCURFCNT_MASK 0x3fff /* refresh interval MASK */
405 #define BCUREVID_REG_W 0x010 /* BCU Revision ID Register (4122>=4101)*/
406 #define BCU81REVID_REG_W 0x014 /* BCU Revision ID Register (=4181)*/
408 #define BCUREVID_RIDMASK (0xf<<12) /* Revision ID */
409 #define BCUREVID_RIDSHFT (12) /* Revision ID */
410 #define BCUREVID_RID_4131 (0x5) /* VR4131 */
411 #define BCUREVID_RID_4122 (0x4) /* VR4122 */
412 #define BCUREVID_RID_4121 (0x3) /* VR4121 */
413 #define BCUREVID_RID_4111 (0x2) /* VR4111 */
414 #define BCUREVID_RID_4102 (0x1) /* VR4102 */
415 #define BCUREVID_RID_4101 (0x0) /* VR4101 */
416 #define BCUREVID_RID_4181 (0x0) /* VR4181 conflict VR4101 */
417 #define BCUREVID_FIXRID_OFF (0x10) /* conflict offset */
418 #define BCUREVID_FIXRID_4181 (0x10) /* VR4181 for kernel */
420 #define BCUREVID_MJREVMASK (0xf<<8) /* Major Revision */
421 #define BCUREVID_MJREVSHFT (8) /* Major Revision */
423 #define BCUREVID_MNREVMASK (0xf) /* Minor Revision */
424 #define BCUREVID_MNREVSHFT (0) /* Minor Revision */
427 #define BCUREFCOUNT_REG_W 0x012 /* BCU Refresh Count Register (>= 4102) */
429 #define BCUREFCOUNT_MASK 0x3fff /* refresh count MASK */
432 #define BCUCLKSPEED_REG_W 0x014 /* Clock Speed Register (>= 4102) */
433 #define BCU81CLKSPEED_REG_W 0x018 /* Clock Speed Register (= 4181) */
435 #define BCUCLKSPEED_DIVT2B (1<<15) /* (= 4102, 4111) */
436 #define BCUCLKSPEED_DIVT3B (1<<14) /* (= 4111) */
437 #define BCUCLKSPEED_DIVT4B (1<<13) /* (= 4111) */
439 #define BCUCLKSPEED_DIVTMASK (0xf<<12) /* (= 4121) */
440 #define BCUCLKSPEED_DIVT3 0x3
441 #define BCUCLKSPEED_DIVT4 0x4
442 #define BCUCLKSPEED_DIVT5 0x5
443 #define BCUCLKSPEED_DIVT6 0x6
444 #define BCUCLKSPEED_DIVTSHFT (12)
446 #define BCUCLKSPEED_TDIVMODE (0x1<<12) /* (= 4122, 4131) */
447 #define BCUCLKSPEED_TDIV4 0x1
448 #define BCUCLKSPEED_TDIV2 0x0
449 #define BCUCLKSPEED_TDIVSHFT (12)
451 #define BCU81CLKSPEED_DIVTMASK (0x7<<13) /* (=4181) */
452 #define BCU81CLKSPEED_DIVT1 0x7
453 #define BCU81CLKSPEED_DIVT2 0x3
454 #define BCU81CLKSPEED_DIVT3 0x5
455 #define BCU81CLKSPEED_DIVT4 0x6
456 #define BCU81CLKSPEED_DIVTSHFT (13)
458 #define BCUCLKSPEED_DIVVTMASK (0xf<<8) /* (= 4121) */
459 #define BCUCLKSPEED_DIVVT1 0x1
460 #define BCUCLKSPEED_DIVVT2 0x2
461 #define BCUCLKSPEED_DIVVT3 0x3
462 #define BCUCLKSPEED_DIVVT4 0x4
463 #define BCUCLKSPEED_DIVVT5 0x5
464 #define BCUCLKSPEED_DIVVT6 0x6
465 #define BCUCLKSPEED_DIVVT1_5 0x9
466 #define BCUCLKSPEED_DIVVT2_5 0xa
467 #define BCUCLKSPEED_DIVVTSHFT (8)
469 #define BCUCLKSPEED_VTDIVMODE (0x7<<8) /* (= 4122, 4131) */
470 #define BCUCLKSPEED_VTDIV6 0x6
471 #define BCUCLKSPEED_VTDIVT5 0x5
472 #define BCUCLKSPEED_VTDIVT4 0x4
473 #define BCUCLKSPEED_VTDIVT3 0x3
474 #define BCUCLKSPEED_VTDIVT2 0x2
475 #define BCUCLKSPEED_VTDIVT1 0x1
476 #define BCUCLKSPEED_VTDIVSHFT (8)
478 #define BCUCLKSPEED_CLKSPMASK (0x1f) /* calculate for Clock */
479 #define BCUCLKSPEED_CLKSPSHFT (0)
481 #define BCUCNT3_REG_W 0x016 /* BCU Control Register 3 (>= 4111) */
483 #define BCUCNT3_EXTROMMASK (1<<15) /* ROM SIZE (4111,4121)*/
484 #define BCUCNT3_EXTROM64M (1<<15) /* 64Mbit DRAM */
485 #define BCUCNT3_EXTROM32M (0<<15) /* 32Mbit DRAM */
487 #define BCUCNT3_EXTDRAMMASK (1<<14) /* DRAM SIZE (4111,4121)*/
488 #define BCUCNT3_EXTDRAM64M (1<<14) /* 64Mbit DRAM */
489 #define BCUCNT3_EXTDRAM16M (0<<14) /* 16Mbit DRAM */
491 #define BCUCNT3_EXTROMCS (0x3<<12) /* Bank3,2 */
492 #define BCUCNT3_ROMROM (0x3<<12) /* Bank3 ROM ,2 ROM */
493 #define BCUCNT3_ROMRAM (0x2<<12) /* Bank3 ROM ,2 RAM */
494 #define BCUCNT3_RAMRAM (0x0<<12) /* Bank3 RAM ,2 RAM */
496 #define BCUCNT3_EXTMEM (1<<11) /* EXT MEN enable (4111,4121)*/
497 #define BCUCNT3_EXTMEMEN (1<<11) /* EXT MEN enable */
498 #define BCUCNT3_EXTMEMDS (0<<11) /* EXT MEN disable */
500 #define BCUCNT3_LCDSIZE (1<<7) /* LCD bus size */
501 #define BCUCNT3_LCD32 (1<<7) /* LCD bus 32bit */
502 #define BCUCNT3_LCD16 (0<<7) /* LCD bus 16bit */
504 #define BCUCNT3_SYSDIREN (1<<3) /* SYSDIR or GPIO6(=4122, 4131)*/
505 #define BCUCNT3_SYSDIR (1<<3) /* SYSDIR */
506 #define BCUCNT3_GPIO6 (0<<3) /* GPIO6 */
508 #define BCUCNT3_LCDSEL1 (1<<1) /* 0xc00-0xdff area buffer (=4122)*/
509 #define BCUCNT3_LCDSEL1_NOBUF (1<<1) /* nobuffer */
510 #define BCUCNT3_LCDSEL1_BUF (0<<1) /* buffer */
512 #define BCUCNT3_LCDSEL0 (1<<1) /* 0xa00-0xbff area buffer (=4122)*/
513 #define BCUCNT3_LCDSEL0_NOBUF (1<<1) /* nobuffer */
514 #define BCUCNT3_LCDSEL0_BUF (0<<1) /* buffer */
