4 * Copyright (c) 1999 SATO Kazumi. All rights reserved.
5 * Copyright (c) 1999 PocketBSD Project. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the PocketBSD project
18 * and its contributors.
19 * 4. Neither the name of the project nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * DCU (DMA Control UNIT) Registers.
41 #define DMARST_REG_W 0x000 /* DMA Reset Register */
42 #define DMARST (1) /* DMA reset */
44 #define DMAIDLE_REG_W 0x002 /* DMA Idle Register */
45 #define DMAISTAT (1) /* DMA Idle Status */
46 #define DMAIDLE (1) /* DMA Idle */
47 #define DMABUSY (0) /* DMA Busy */
50 #define DMASEN_REG_W 0x004 /* DMA Sequencer Enable Register */
51 #define DMASENMASK (1) /* DMA Seq Enable */
52 #define DMASEN (1) /* DMA Seq Enable */
53 #define DMASDS (0) /* DMA Seq Disable */
56 #define DMAMSK_REG_W 0x006 /* DMA Mask Register */
57 #define DMAMSKAIN (1<<3) /* Audio IN DMA Enable */
58 #define DMAMSKAOUT (1<<2) /* Audio OUT DMA Enable */
59 #define DMAMSKFOUT (1) /* FIR DMA Enable */
62 #define DMAREQ_REG_W 0x008 /* DMA Request Register */
63 #define DMAREQAIN (1<<3) /* Audio IN Request pending */
64 #define DMAREQAOUT (1<<2) /* Audio OUT Request pending */
65 #define DMAREQFOUT (1) /* FIR Request pending */
68 #define DMATD_REG_W 0x00A /* DMA Transfer Direction Register */
69 #define DMATDMASK (1) /* DMA transfer direction (FIR) */
70 #define DMATDIOMEM (1) /* I/O -> MEM */
71 #define DMATDMEMIO (0) /* MEM -> I/O */