sys/arch/hpcmips/vr/icureg.h

   1 /*      $NetBSD: icureg.h,v 1.7 2002/02/11 11:44:36 takemura Exp $      */
   2
   3 /*-
   4  * Copyright (c) 1999 Shin Takemura. All rights reserved.
   5  * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
   6  * Copyright (c) 1999 PocketBSD Project. All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by the PocketBSD project
  19  *      and its contributors.
  20  * 4. Neither the name of the project nor the names of its contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGE.
  35  *
  36  */
  37
  38 /*
  39  *      ICU (Interrupt Control UNIT) Registers definitions
  40  *              start 0x0A000080 (vr4181)
  41  *              start 0x0B000080 (vr4102/4111/4121)
  42  *              start 0x0F000080 (vr4122)
  43  */
  44 #include "opt_vr41xx.h"
  45 #include <hpcmips/vr/vrcpudef.h>
  46
  47 #define ICU_NO_REG_W            0xffffffff      /* no register */
  48
  49
  50 /* SYSINT1 & MSYSINT1 */
  51 #define SYSINT1_REG_W           0x000   /* Level1 System intr reg 1 */
  52 #define MSYSINT1_REG_W          0x00c   /* Level1 Mask System intr reg 1 */
  53
  54 #define SYSINT1_INT15                   (1<<15)
  55 #define SYSINT1_INT14                   (1<<14)
  56 #define SYSINT1_INT13                   (1<<13)
  57 #define SYSINT1_DOZEPIU                 (1<<13) /* PIU intr during Suspend */
  58 #define SYSINT1_INT12                   (1<<12)
  59 #define SYSINT1_CLKRUN                  (1<<12) /* CLKRUN intr (=vr4122) */
  60 #define SYSINT1_INT11                   (1<<11)
  61 #define SYSINT1_SOFT                    (1<<11) /* Software intr */
  62 #define SYSINT1_INT10                   (1<<10)
  63 #define SYSINT1_WRBERR                  (1<<10) /* Bus error intr (4102 <=,<= 4121)*/
  64 #define SYSINT1_INT9                    (1<<9)
  65 #define SYSINT1_SIU                     (1<<9)  /* SIU intr */
  66 #define SYSINT1_INT8                    (1<<8)
  67 #define SYSINT1_GIU                     (1<<8)  /* GIU intr */
  68 #define SYSINT1_INT7                    (1<<7)
  69 #define SYSINT1_KIU                     (1<<7)  /* KIU intr (4102 <=,<= 4121)*/
  70 #define SYSINT1_INT6                    (1<<6)
  71 #define SYSINT1_AIU                     (1<<6)  /* AIU intr (4102 <=,<= 4121)*/
  72 #define SYSINT1_INT5                    (1<<5)
  73 #define SYSINT1_PIU                     (1<<5)  /* PIU intr (4102 <=,<= 4121)*/
  74 #define SYSINT1_INT4                    (1<<4)
  75 #define SYSINT1_INT3                    (1<<3)
  76 #define SYSINT1_ETIMER                  (1<<3)  /* ETIMER intr */
  77 #define SYSINT1_INT2                    (1<<2)
  78 #define SYSINT1_RTCL1                   (1<<2)  /* RTClong1 intr */
  79 #define SYSINT1_INT1                    (1<<1)
  80 #define SYSINT1_POWER                   (1<<1)  /* PowerSW intr */
  81 #define SYSINT1_INT0                    (1<<0)
  82 #define SYSINT1_BAT                     (1<<0)  /* Battery intr */
  83
  84
  85 /* PIUINT & MPIUINT */
  86 #define ICUPIUINT_REG_W         0x002   /* Level2 PIU intr reg */
  87 #define MPIUINT_REG_W           0x00e   /* Level2 Mask PIU intr reg */
  88
  89 #define         PIUINT_PADCMD           (1<<6)  /* PIU command scan intr */
  90 #define         PIUINT_PADADP           (1<<5)  /* PIU AD port scan intr */
  91 #define         PIUINT_PADPAGE1         (1<<4)  /* PIU data page 1 intr */
  92 #define         PIUINT_PADPAGE0         (1<<3)  /* PIU data page 0 intr */
  93 #define         PIUINT_PADLOST          (1<<2)  /* A/D data timeout intr */
  94 #define         PIUINT_PENCHG           (1)     /* Touch Panel contact intr */
  95
  96
  97 /* AIUINT & MAIUINT */
  98 #define VR4102_AIUINT_REG_W     0x004   /* Level2 AIU intr reg */
  99 #define VR4102_MAIUINT_REG_W    0x010   /* Level2 Mask AIU intr reg */
 100 #define VR4122_AIUINT_REG_W     ICU_NO_REG_W    /* Level2 AIU intr reg */
 101 #define VR4122_MAIUINT_REG_W    ICU_NO_REG_W    /* Level2 Mask AIU intr reg */
 102 #define VR4181_AIUINT_REG_W     0x004   /* Level2 AIU intr reg */
 103 #define VR4181_MAIUINT_REG_W    0x010   /* Level2 Mask AIU intr reg */
 104 #if defined SINGLE_VRIP_BASE
 105 #if defined VRGROUP_4102_4121
 106 #define AIUINT_REG_W            VR4102_AIUINT_REG_W
 107 #define MAIUINT_REG_W           VR4102_MAIUINT_REG_W
 108 #endif /* VRGROUP_4102_4121 */
 109 #if defined VRGROUP_4122_4131
 110 #define AIUINT_REG_W            VR4122_AIUINT_REG_W
 111 #define MAIUINT_REG_W           VR4122_MAIUINT_REG_W
 112 #endif /* VRGROUP_4122_4131 */
 113 #if defined VRGROUP_4181
 114 #define AIUINT_REG_W            VR4181_AIUINT_REG_W
 115 #define MAIUINT_REG_W           VR4181_MAIUINT_REG_W
 116 #endif /* VRGROUP_4181 */
 117 #endif
 118
 119 #define         AIUINT_INTMEND          (1<<11) /* Audio input DMA buffer 2 page */
 120 #define         AIUINT_INTM             (1<<10) /* Audio input DMA buffer 1 page */
 121 #define         AIUINT_INTMIDLE         (1<<9)  /* Audio input idle intr */
 122 #define         AIUINT_INTMST           (1<<8)  /* Audio input receive completion intr */
 123 #define         AIUINT_INTSEND          (1<<3)  /* Audio output buffer 2 page */
 124 #define         AIUINT_INTS             (1<<2)  /* Audio output buffer 1 page */
 125 #define         AIUINT_INTSIDLE         (1<<1)  /* Audio output idle intr */
 126
 127
 128 /* KIUINT & MKIUINT */
 129 #define VR4102_KIUINT_REG_W     0x006   /* Level2 KIU intr reg */
 130 #define VR4102_MKIUINT_REG_W    0x012   /* Level2 Mask KIU intr reg */
 131 #define VR4122_KIUINT_REG_W     ICU_NO_REG_W    /* Level2 KIU intr reg */
 132 #define VR4122_MKIUINT_REG_W    ICU_NO_REG_W    /* Level2 Mask KIU intr reg */
 133 #define VR4181_KIUINT_REG_W     0x118   /* Level2 KIU intr reg */
 134 #define VR4181_MKIUINT_REG_W    0x012   /* Level2 Mask KIU intr reg */
 135 #if defined SINGLE_VRIP_BASE
 136 #if defined VRGROUP_4102_4121
 137 #define KIUINT_REG_W            VR4102_KIUINT_REG_W
 138 #define MKIUINT_REG_W           VR4102_MKIUINT_REG_W
 139 #endif /* VRGROUP_4102_4121 */
 140 #if defined VRGROUP_4122_4131
 141 #define KIUINT_REG_W            VR4122_KIUINT_REG_W
 142 #define MKIUINT_REG_W           VR4122_MKIUINT_REG_W
 143 #endif /* VRGROUP_4122_4131 */
 144 #if defined VRGROUP_4181
 145 #define KIUINT_REG_W            VR4181_KIUINT_REG_W
 146 #define MKIUINT_REG_W           VR4181_MKIUINT_REG_W
 147 #endif /* VRGROUP_4181 */
 148 #endif
 149
 150 #define         KIUINT_KDATLOST         (1<<2)  /* Key scan data lost */
 151 #define         KIUINT_KDATRDY          (1<<1)  /* Key scan data complete */
 152 #define         KIUINT_SCANINT          (1)     /* Key input detect intr */
 153
 154
 155 /* GIUINTL & MGIUINTL */
 156 #define VR4102_GIUINT_L_REG_W   0x008   /* Level2 GIU intr reg Low */
 157 #define VR4102_MGIUINT_L_REG_W  0x014   /* Level2 Mask GIU intr reg Low */
 158 #define VR4122_GIUINT_L_REG_W   0x008   /* Level2 GIU intr reg Low */
 159 #define VR4122_MGIUINT_L_REG_W  0x014   /* Level2 Mask GIU intr reg Low */
 160 #define VR4181_GIUINT_L_REG_W   ICU_NO_REG_W    /* Level2 GIU intr reg Low */
 161 #define VR4181_MGIUINT_L_REG_W  ICU_NO_REG_W    /* Level2 Mask GIU intr reg Low */
 162 #if defined SINGLE_VRIP_BASE
 163 #if defined VRGROUP_4102_4121
 164 #define GIUINT_L_REG_W          VR4102_GIUINT_L_REG_W
 165 #define MGIUINT_L_REG_W         VR4102_MGIUINT_L_REG_W
 166 #endif /* VRGROUP_4102_4121 */
 167 #if defined VRGROUP_4122_4131
 168 #define GIUINT_L_REG_W          VR4122_GIUINT_L_REG_W
 169 #define MGIUINT_L_REG_W         VR4122_MGIUINT_L_REG_W
 170 #endif /* VRGROUP_4122_4131 */
 171 #if defined VRGROUP_4181
 172 #define GIUINT_L_REG_W          VR4181_GIUINT_L_REG_W
 173 #define MGIUINT_L_REG_W         VR4181_MGIUINT_L_REG_W
 174 #endif /* VRGROUP_4181 */
 175 #endif
 176
 177 #define         GIUINT_GPIO15           (1<<15) /* GPIO 15 */
 178 #define         GIUINT_GPIO14           (1<<14) /* GPIO 14 */
 179 #define         GIUINT_GPIO13           (1<<13) /* GPIO 13 */
 180 #define         GIUINT_GPIO12           (1<<12) /* GPIO 12 */
 181 #define         GIUINT_GPIO11           (1<<11) /* GPIO 11 */
 182 #define         GIUINT_GPIO10           (1<<10) /* GPIO 10 */
 183 #define         GIUINT_GPIO9            (1<<9)  /* GPIO 9 */
 184 #define         GIUINT_GPIO8            (1<<8)  /* GPIO 8 */
 185 #define         GIUINT_GPIO7            (1<<7)  /* GPIO 7 */
 186 #define         GIUINT_GPIO6            (1<<6)  /* GPIO 6 */
 187 #define         GIUINT_GPIO5            (1<<5)  /* GPIO 5 */
 188 #define         GIUINT_GPIO4            (1<<4)  /* GPIO 4 */
 189 #define         GIUINT_GPIO3            (1<<3)  /* GPIO 3 */
 190 #define         GIUINT_GPIO2            (1<<2)  /* GPIO 2 */
 191 #define         GIUINT_GPIO1            (1<<1)  /* GPIO 1 */
 192 #define         GIUINT_GPIO0            (1)     /* GPIO 0 */
 193
 194
 195 /* DSIUINT & MDSIUINT */
 196 #define VR4102_DSIUINT_REG_W            0x00a   /* Level2 DSIU intr reg */
 197 #define VR4102_MDSIUINT_REG_W           0x016   /* Level2 Mask DSIU intr reg */
 198 #define VR4122_DSIUINT_REG_W            0x00a   /* Level2 DSIU intr reg */
 199 #define VR4122_MDSIUINT_REG_W           0x016   /* Level2 Mask DSIU intr reg */
 200 #define VR4181_DSIUINT_REG_W            ICU_NO_REG_W    /* Level2 DSIU intr reg */
 201 #define VR4181_MDSIUINT_REG_W           ICU_NO_REG_W    /* Level2 Mask DSIU intr reg */
 202 #if defined SINGLE_VRIP_BASE
 203 #if defined VRGROUP_4102_4121
 204 #define DSIUINT_REG_W           VR4102_DSIUINT_REG_W
 205 #define MDSIUINT_REG_W          VR4102_MDSIUINT_REG_W
 206 #endif /* VRGROUP_4102_4121 */
 207 #if defined VRGROUP_4122_4131
 208 #define DSIUINT_REG_W           VR4122_DSIUINT_REG_W
 209 #define MDSIUINT_REG_W          VR4122_MDSIUINT_REG_W
 210 #endif /* VRGROUP_4122_4131 */
 211 #if defined VRGROUP_4181
 212 #define DSIUINT_REG_W           VR4181_DSIUINT_REG_W
 213 #define MDSIUINT_REG_W          VR4181_MDSIUINT_REG_W
 214 #endif /* VRGROUP_4181 */
 215 #endif
 216
 217 #define         DSIUINT_DCTS            (1<<11) /* DCTS# change */
 218 #define         DSIUINT_SER0            (1<<10) /* Debug serial receive error */
 219 #define         DSIUINT_SR0             (1<<9)  /* Debug serial receive */
 220 #define         DSIUINT_ST0             (1<<8)  /* Debug serial transmit */
 221
 222
 223 /* NMI */
 224 #define NMI_REG_W               0x018   /* NMI reg */
 225
 226 #define         LOWBATT_NMIORINT        (1)     /* Low battery type */
 227 #define         LOWBATT_INT0            (1)     /* Low battery int 0 */
 228 #define         LOWBATT_NMI             (0)     /* Low battery NMI */
 229
 230
 231 /* SOFTINT */
 232 #define SOFTINT_REG_W           0x01a   /* Software intr reg */
 233
 234 #define         SOFTINT_MASK3           (1<<3)  /* Softint3 mask */
 235 #define         SOFTINT_SET3            (1<<3)  /* Softint3 set */
 236 #define         SOFTINT_CLEAR3          (0<<3)  /* Softint3 clear */
 237
 238 #define         SOFTINT_MASK2           (1<<2)  /* Softint2 mask */
 239 #define         SOFTINT_SET2            (1<<2)  /* Softint2 set */
 240 #define         SOFTINT_CLEAR2          (0<<2)  /* Softint2 clear */
 241
 242 #define         SOFTINT_MASK1           (1<<1)  /* Softint1 mask */
 243 #define         SOFTINT_SET1            (1<<1)  /* Softint1 set */
 244 #define         SOFTINT_CLEAR1          (0<<1)  /* Softint1 clear */
 245
 246 #define         SOFTINT_MASK0           (1)     /* Softint0 mask */
 247 #define         SOFTINT_SET0            (1)     /* Softint0 set */
 248 #define         SOFTINT_CLEAR0          (0)     /* Softint0 clear */
 249
 250
 251 /* SYSINT2 & MSYSINT2 */
 252 #define VR4102_SYSINT2_REG_W    0x180   /* Level1 System intr reg 2 */
 253 #define VR4102_MSYSINT2_REG_W   0x186   /* Level1 Mask System intr reg 2 */
 254 #define VR4122_SYSINT2_REG_W    0x020   /* Level1 System intr reg 2 */
 255 #define VR4122_MSYSINT2_REG_W   0x026   /* Level1 Mask System intr reg 2 */
 256 #define VR4181_SYSINT2_REG_W    0x180   /* Level1 System intr reg 2 */
 257 #define VR4181_MSYSINT2_REG_W   0x186   /* Level1 Mask System intr reg 2 */
 258 #if defined SINGLE_VRIP_BASE
 259 #if defined VRGROUP_4102_4121
 260 #define SYSINT2_REG_W           VR4102_SYSINT2_REG_W
 261 #define MSYSINT2_REG_W          VR4102_MSYSINT2_REG_W
 262 #endif /* VRGROUP_4102_4121 */
 263 #if defined VRGROUP_4122_4131
 264 #define SYSINT2_REG_W           VR4122_SYSINT2_REG_W
 265 #define MSYSINT2_REG_W          VR4122_MSYSINT2_REG_W
 266 #endif /* VRGROUP_4122_4131 */
 267 #if defined VRGROUP_4181
 268 #define SYSINT2_REG_W           VR4181_SYSINT2_REG_W
 269 #define MSYSINT2_REG_W          VR4181_MSYSINT2_REG_W
 270 #endif /* VRGROUP_4181 */
 271 #endif
 272
 273 #define SYSINT2_INT31                   (1<<15)
 274 #define SYSINT2_INT30                   (1<<14)
 275 #define SYSINT2_INT29                   (1<<13)
 276 #define SYSINT2_INT28                   (1<<12)
 277 #define SYSINT2_INT27                   (1<<11)
 278 #define SYSINT2_INT26                   (1<<10)
 279 #define SYSINT2_INT25                   (1<<9)
 280 #define SYSINT2_BCU                     (1<<9)  /* BCU intr (=vr4122) */
 281 #define SYSINT2_INT24                   (1<<8)
 282 #define SYSINT2_CSI                     (1<<8)  /* CSI intr (=vr4122) */
 283 #define SYSINT2_INT23                   (1<<7)
 284 #define SYSINT2_SCU                     (1<<7)  /* SCU intr (=vr4122) */
 285 #define SYSINT2_INT22                   (1<<6)
 286 #define SYSINT2_PCI                     (1<<6)  /* PCI intr (=vr4122) */
 287 #define SYSINT2_LCD                     (1<<6)  /* LCD intr (=vr4181) */
 288 #define SYSINT2_DSIU                    (1<<5)  /* DSUI intr */
 289 #define SYSINT2_DCU81                   (1<<5)  /* DCU intr (=4181) */
 290 #define SYSINT2_FIR                     (1<<4)  /* FIR intr */
 291 #define SYSINT2_TCLK                    (1<<3)  /* TClock Counter intr */
 292 #define SYSINT2_CSI81                   (1<<3)  /* CSI intr (=4181) */
 293 #define SYSINT2_HSP                     (1<<2)  /* HSP intr (4122>=4102)*/
 294 #define SYSINT2_ECU                     (1<<2)  /* EUC intr (=4181)*/
 295 #define SYSINT2_LED                     (1<<1)  /* LED intr */
 296 #define SYSINT2_RTCL2                   (1<<0)  /* RTCLong2 intr */
 297
 298
 299 /* GIUINTH & MGIUINTH */
 300 #define VR4102_GIUINT_H_REG_W   0x182   /* Level2 GIU intr reg High */
 301 #define VR4102_MGIUINT_H_REG_W  0x188   /* Level2 Mask GIU intr reg High */
 302 #define VR4122_GIUINT_H_REG_W   0x022   /* Level2 GIU intr reg High */
 303 #define VR4122_MGIUINT_H_REG_W  0x028   /* Level2 Mask GIU intr reg High */
 304 #define VR4181_GIUINT_H_REG_W   ICU_NO_REG_W    /* Level2 GIU intr reg High */
 305 #define VR4181_MGIUINT_H_REG_W  ICU_NO_REG_W    /* Level2 Mask GIU intr reg High */
 306 #if defined SINGLE_VRIP_BASE
 307 #if defined VRGROUP_4102_4121
 308 #define GIUINT_H_REG_W          VR4102_GIUINT_H_REG_W
 309 #define MGIUINT_H_REG_W         VR4102_MGIUINT_H_REG_W
 310 #endif /* VRGROUP_4102_4121 */
 311 #if defined VRGROUP_4122_4131
 312 #define GIUINT_H_REG_W          VR4122_GIUINT_H_REG_W
 313 #define MGIUINT_H_REG_W         VR4122_MGIUINT_H_REG_W
 314 #endif /* VRGROUP_4122_4131 */
 315 #if defined VRGROUP_4181
 316 #define GIUINT_H_REG_W          VR4181_GIUINT_H_REG_W
 317 #define MGIUINT_H_REG_W         VR4181_MGIUINT_H_REG_W
 318 #endif /* VRGROUP_4181 */
 319 #endif
 320
 321 #define         GIUINT_GPIO31           (1<<15) /* GPIO 31 */
 322 #define         GIUINT_GPIO30           (1<<14) /* GPIO 30 */
 323 #define         GIUINT_GPIO29           (1<<13) /* GPIO 29 */
 324 #define         GIUINT_GPIO28           (1<<12) /* GPIO 28 */
 325 #define         GIUINT_GPIO27           (1<<11) /* GPIO 27 */
 326 #define         GIUINT_GPIO26           (1<<10) /* GPIO 26 */
 327 #define         GIUINT_GPIO25           (1<<9)  /* GPIO 25 */
 328 #define         GIUINT_GPIO24           (1<<8)  /* GPIO 24 */
 329 #define         GIUINT_GPIO23           (1<<7)  /* GPIO 23 */
 330 #define         GIUINT_GPIO22           (1<<6)  /* GPIO 22 */
 331 #define         GIUINT_GPIO21           (1<<5)  /* GPIO 21 */
 332 #define         GIUINT_GPIO20           (1<<4)  /* GPIO 20 */
 333 #define         GIUINT_GPIO19           (1<<3)  /* GPIO 19 */
 334 #define         GIUINT_GPIO18           (1<<2)  /* GPIO 18 */
 335 #define         GIUINT_GPIO17           (1<<1)  /* GPIO 17 */
 336 #define         GIUINT_GPIO16           (1)     /* GPIO 16 */
 337
 338
 339 /* FIRINT & MFIRINT */
 340 #define VR4102_FIRINT_REG_W     0x184   /* Level2 FIR intr reg */
 341 #define VR4102_MFIRINT_REG_W    0x18a   /* Level2 Mask FIR intr reg */
 342 #define VR4122_FIRINT_REG_W     0x024   /* Level2 FIR intr reg */
 343 #define VR4122_MFIRINT_REG_W    0x02a   /* Level2 Mask FIR intr reg */
 344 #define VR4181_FIRINT_REG_W     ICU_NO_REG_W    /* Level2 FIR intr reg */
 345 #define VR4181_MFIRINT_REG_W    ICU_NO_REG_W    /* Level2 Mask FIR intr reg */
 346 #if defined SINGLE_VRIP_BASE
 347 #if defined VRGROUP_4102_4121
 348 #define FIRINT_REG_W            VR4102_FIRINT_REG_W
 349 #define MFIRINT_REG_W           VR4102_MFIRINT_REG_W
 350 #endif /* VRGROUP_4102_4121 */
 351 #if defined VRGROUP_4122_4131
 352 #define FIRINT_REG_W            VR4122_FIRINT_REG_W
 353 #define MFIRINT_REG_W           VR4122_MFIRINT_REG_W
 354 #endif /* VRGROUP_4122_4131 */
 355 #if defined VRGROUP_4181
 356 #define FIRINT_REG_W            VR4181_FIRINT_REG_W
 357 #define MFIRINT_REG_W           VR4181_MFIRINT_REG_W
 358 #endif /* VRGROUP_4181 */
 359 #endif
 360
 361 #define         FIRINT_FIR              (1<<4)  /* FIR intr */
 362 #define         FIRINT_RECV2            (1<<3)  /* FIR DMA buf recv buffer2 */
 363 #define         FIRINT_TRNS2            (1<<2)  /* FIR DMA buf transmit buffer2 */
 364 #define         FIRINT_RECV1            (1<<1)  /* FIR DMA buf recv buffer1 */
 365 #define         FIRINT_TRNS1            (1)     /* FIR DMA buf transmit buffer1 */
 366
 367
 368 /* PCIINT & MPCIINT */
 369 #define VR4102_PCIINT_REG_W     ICU_NO_REG_W    /* Level2 PCI intr reg */
 370 #define VR4102_MPCIINT_REG_W    ICU_NO_REG_W    /* Level2 PCI intr mask */
 371 #define VR4122_PCIINT_REG_W     0x2c    /* Level2 PCI intr reg */
 372 #define VR4122_MPCIINT_REG_W    0x32    /* Level2 PCI intr mask */
 373 #define VR4181_PCIINT_REG_W     ICU_NO_REG_W    /* Level2 PCI intr reg */
 374 #define VR4181_MPCIINT_REG_W    ICU_NO_REG_W    /* Level2 PCI intr mask */
 375 #if defined SINGLE_VRIP_BASE
 376 #if defined VRGROUP_4102_4121
 377 #define PCIINT_REG_W            VR4102_PCIINT_REG_W
 378 #define MPCIINT_REG_W           VR4102_MPCIINT_REG_W
 379 #endif /* VRGROUP_4102_4121 */
 380 #if defined VRGROUP_4122_4131
 381 #define PCIINT_REG_W            VR4122_PCIINT_REG_W
 382 #define MPCIINT_REG_W           VR4122_MPCIINT_REG_W
 383 #endif /* VRGROUP_4122_4131 */
 384 #if defined VRGROUP_4181
 385 #define PCIINT_REG_W            VR4181_PCIINT_REG_W
 386 #define MPCIINT_REG_W           VR4181_MPCIINT_REG_W
 387 #endif /* VRGROUP_4181 */
 388 #endif
 389
 390 #define         PCIINT_INT0             (1)     /* PCI INT 0 */
 391
 392
 393 /* SCUINT & MSCUINT */
 394 #define VR4102_SCUINT_REG_W     ICU_NO_REG_W    /* Level2 SCU intr reg */
 395 #define VR4102_MSCUINT_REG_W    ICU_NO_REG_W    /* Level2 SCU intr mask */
 396 #define VR4122_SCUINT_REG_W     0x2e    /* Level2 SCU intr reg */
 397 #define VR4122_MSCUINT_REG_W    0x34    /* Level2 SCU intr mask */
 398 #define VR4181_SCUINT_REG_W     ICU_NO_REG_W    /* Level2 SCU intr reg */
 399 #define VR4181_MSCUINT_REG_W    ICU_NO_REG_W    /* Level2 SCU intr mask */
 400 #if defined SINGLE_VRIP_BASE
 401 #if defined VRGROUP_4102_4121
 402 #define SCUINT_REG_W            VR4102_SCUINT_REG_W
 403 #define MSCUINT_REG_W           VR4102_MSCUINT_REG_W
 404 #endif /* VRGROUP_4102_4121 */
 405 #if defined VRGROUP_4122_4131
 406 #define SCUINT_REG_W            VR4122_SCUINT_REG_W
 407 #define MSCUINT_REG_W           VR4122_MSCUINT_REG_W
 408 #endif /* VRGROUP_4122_4131 */
 409 #if defined VRGROUP_4181
 410 #define SCUINT_REG_W            VR4181_SCUINT_REG_W
 411 #define MSCUINT_REG_W           VR4181_MSCUINT_REG_W
 412 #endif /* VRGROUP_4181 */
 413 #endif
 414
 415 #define         SCUINT_INT0             (1)     /* SCU INT 0 */
 416
 417
 418 /* CSIINT & MCSIINT */
 419 #define VR4102_CSIINT_REG_W     ICU_NO_REG_W    /* Level2 CSI intr reg */
 420 #define VR4102_MCSIINT_REG_W    ICU_NO_REG_W    /* Level2 CSI intr mask */
 421 #define VR4122_CSIINT_REG_W     0x30    /* Level2 CSI intr reg */
 422 #define VR4122_MCSIINT_REG_W    0x36    /* Level2 CSI intr mask */
 423 #define VR4181_CSIINT_REG_W     ICU_NO_REG_W    /* Level2 CSI intr reg */
 424 #define VR4181_MCSIINT_REG_W    ICU_NO_REG_W    /* Level2 CSI intr mask */
 425 #if defined SINGLE_VRIP_BASE
 426 #if defined VRGROUP_4102_4121
 427 #define CSIINT_REG_W            VR4102_CSIINT_REG_W
 428 #define MCSIINT_REG_W           VR4102_MCSIINT_REG_W
 429 #endif /* VRGROUP_4102_4121 */
 430 #if defined VRGROUP_4122_4131
 431 #define CSIINT_REG_W            VR4122_CSIINT_REG_W
 432 #define MCSIINT_REG_W           VR4122_MCSIINT_REG_W
 433 #endif /* VRGROUP_4122_4131 */
 434 #if defined VRGROUP_4181
 435 #define CSIINT_REG_W            VR4181_CSIINT_REG_W
 436 #define MCSIINT_REG_W           VR4181_MCSIINT_REG_W
 437 #endif /* VRGROUP_4181 */
 438 #endif
 439
 440 #define         CSIINT_TRPAGE2          (1<<6)  /* DMA send page 2 intr */
 441 #define         CSIINT_TRPAGE1          (1<<5)  /* DMA send page 1 intr */
 442 #define         CSIINT_TREND            (1<<4)  /* send every data intr */
 443 #define         CSIINT_TREMPTY          (1<<3)  /* send FIFO empty intr */
 444 #define         CSIINT_RCPAGE2          (1<<2)  /* DMA recv page 2 intr */
 445 #define         CSIINT_RCPAGE1          (1<<1)  /* DMA recv page 1 intr */
 446 #define         CSIINT_RCOVER           (1)     /* recv FIFO overrun intr */
 447
 448
 449 /* BCUINT & MBCUINT */
 450 #define VR4102_BCUINT_REG_W     ICU_NO_REG_W    /* Level2 BCU intr reg */
 451 #define VR4102_MBCUINT_REG_W    ICU_NO_REG_W    /* Level2 BCU intr mask */
 452 #define VR4122_BCUINT_REG_W     0x38    /* Level2 BCU intr reg */
 453 #define VR4122_MBCUINT_REG_W    0x3a    /* Level2 BCU intr mask */
 454 #define VR4181_BCUINT_REG_W     ICU_NO_REG_W    /* Level2 BCU intr reg */
 455 #define VR4181_MBCUINT_REG_W    ICU_NO_REG_W    /* Level2 BCU intr mask */
 456 #if defined SINGLE_VRIP_BASE
 457 #if defined VRGROUP_4102_4121
 458 #define BCUINT_REG_W            VR4102_BCUINT_REG_W
 459 #define MBCUINT_REG_W           VR4102_MBCUINT_REG_W
 460 #endif /* VRGROUP_4102_4121 */
 461 #if defined VRGROUP_4122_4131
 462 #define BCUINT_REG_W            VR4122_BCUINT_REG_W
 463 #define MBCUINT_REG_W           VR4122_MBCUINT_REG_W
 464 #endif /* VRGROUP_4122_4131 */
 465 #if defined VRGROUP_4181
 466 #define BCUINT_REG_W            VR4181_BCUINT_REG_W
 467 #define MBCUINT_REG_W           VR4181_MBCUINT_REG_W
 468 #endif /* VRGROUP_4181 */
 469 #endif
 470
 471 #define         BCUINT_INT              (1)     /* BCU INT */
 472
 473 /* END icureg.h */