sys/arch/hpcmips/vr/rtcreg.h

   1 /*      $NetBSD: rtcreg.h,v 1.8 2002/02/10 14:36:52 sato Exp $  */
   2
   3 /*-
   4  * Copyright (c) 1999 Shin Takemura. All rights reserved.
   5  * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
   6  * Copyright (c) 1999 PocketBSD Project. All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by the PocketBSD project
  19  *      and its contributors.
  20  * 4. Neither the name of the project nor the names of its contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGE.
  35  *
  36  */
  37
  38 #define EPOCHOFF        0                       /* epoch offset */
  39 #ifndef EPOCHYEAR
  40 #define EPOCHYEAR       1850    /* XXX */       /* WINCE epoch year */
  41 #endif
  42 #define EPOCHMONTH      1                       /* WINCE epoch month of year */
  43 #define EPOCHDATE       1                       /* WINCE epoch date of month */
  44
  45 #define LEAPYEAR4(year) ((((year) % 4) == 0 && ((year) % 100) != 0) || ((year%400)) == 0)
  46 #define LEAPYEAR2(year) (((year) % 4) == 0)
  47
  48 /*
  49  *      RTC (Real Time Clock Unit) Registers definitions.
  50  *              start 0x0B0000C0 (Vr4102-4121)
  51  *              start 0x0F000100 (Vr4122-4131)
  52  *              start 0x0B0000C0 (Vr4181)
  53  */
  54 #define RTC_NO_REG_W            0xffffffff
  55
  56 #define ETIME_L_REG_W           0x000   /* Elapsed Time L */
  57 #define ETIME_M_REG_W           0x002   /* Elapsed Time M */
  58 #define ETIME_H_REG_W           0x004   /* Elapsed Time H */
  59
  60 #define         ETIME_L_HZ              0x8000  /* 1 HZ */
  61
  62
  63 #define ECMP_L_REG_W            0x008   /* Elapsed Compare L */
  64 #define ECMP_M_REG_W            0x00a   /* Elapsed Compare M */
  65 #define ECMP_H_REG_W            0x00c   /* Elapsed Compare H */
  66
  67
  68 #define RTCL1_L_REG_W           0x010   /* RTC Long 1 L */
  69 #define RTCL1_H_REG_W           0x012   /* RTC Long 1 H */
  70
  71 #define         RTCL1_L_HZ              0x8000  /* 1 HZ */
  72
  73
  74 #define RTCL1_CNT_L_REG_W       0x014   /* RTC Long 1 Count L */
  75 #define RTCL1_CNT_H_REG_W       0x016   /* RTC Long 1 Count H */
  76
  77
  78 #define RTCL2_L_REG_W           0x018   /* RTC Long 2 L */
  79 #define RTCL2_H_REG_W           0x01a   /* RTC Long 2 H */
  80
  81 #define         RTCL2_L_HZ              0x8000  /* 1 HZ */
  82
  83
  84 #define RTCL2_CNT_L_REG_W       0x01c   /* RTC Long 2 Count L */
  85 #define RTCL2_CNT_H_REG_W       0x01e   /* RTC Long 2 Count H */
  86
  87
  88 #define VR4102_TCLK_L_REG_W     0x100   /* TCLK L */
  89 #define VR4102_TCLK_H_REG_W     0x102   /* TCLK H */
  90 #define VR4122_TCLK_L_REG_W     0x020   /* TCLK L */
  91 #define VR4122_TCLK_H_REG_W     0x022   /* TCLK H */
  92 #if defined SINGLE_VRIP_BASE
  93 #if defined VRGROUP_4102_4121
  94 #define TCLK_L_REG_W            VR4102_TCLK_L_REG_W     /* TCLK L */
  95 #define TCLK_H_REG_W            VR4102_TCLK_H_REG_W     /* TCLK H */
  96 #endif /* VRGROUP_4102_4121 */
  97 #if defined VRGROUP_4122_4131
  98 #define TCLK_L_REG_W            VR4122_TCLK_L_REG_W     /* TCLK L */
  99 #define TCLK_H_REG_W            VR4122_TCLK_H_REG_W     /* TCLK H */
 100 #endif /* VRGROUP_4122_4131 */
 101 #if defined VRGROUP_4181
 102 #define TCLK_L_REG_W            RTC_NO_REG_W
 103 #define TCLK_H_REG_W            RTC_NO_REG_W
 104 #endif /* VRGROUP_4181 */
 105 #endif /* defined SINGLE_VRIP_BASE */
 106
 107
 108 #define VR4102_TCLK_CNT_L_REG_W 0x104   /* TCLK Count L */
 109 #define VR4102_TCLK_CNT_H_REG_W 0x106   /* TCLK Count H */
 110 #define VR4122_TCLK_CNT_L_REG_W 0x024   /* TCLK Count L */
 111 #define VR4122_TCLK_CNT_H_REG_W 0x026   /* TCLK Count H */
 112 #if defined SINGLE_VRIP_BASE
 113 #if defined VRGROUP_4102_4121
 114 #define TCLK_CNT_L_REG_W        VR4102_TCLK_CNT_L_REG_W /* TCLK Count L */
 115 #define TCLK_CNT_H_REG_W        VR4102_TCLK_CNT_L_REG_W /* TCLK Count H */
 116 #endif /* VRGROUP_4102_4121 */
 117 #if defined VRGROUP_4122_4131
 118 #define TCLK_CNT_L_REG_W        VR4122_TCLK_CNT_L_REG_W /* TCLK Count L */
 119 #define TCLK_CNT_H_REG_W        VR4122_TCLK_CNT_H_REG_W /* TCLK Count H */
 120 #endif /* VRGROUP_4122_4131 */
 121 #if defined VRGROUP_4181
 122 #define TCLK_CNT_L_REG_W        RTC_NO_REG_W
 123 #define TCLK_CNT_H_REG_W        RTC_NO_REG_W
 124 #endif /* VRGROUP_4181 */
 125 #endif /* defined SINGLE_VRIP_BASE */
 126
 127
 128 #define VR4102_RTCINT_REG_W             0x11e   /* RTC intr reg. */
 129 #define VR4122_RTCINT_REG_W             0x03e   /* RTC intr reg. */
 130 #define VR4181_RTCINT_REG_W             0x11e   /* RTC intr reg. */
 131 #if defined SINGLE_VRIP_BASE
 132 #if defined VRGROUP_4102_4121
 133 #define RTCINT_REG_W            VR4102_RTCINT_REG_W     /* RTC intr reg. */
 134 #endif /* VRGROUP_4102_4121 */
 135 #if defined VRGROUP_4122_4131
 136 #define RTCINT_REG_W            VR4122_RTCINT_REG_W     /* RTC intr reg. */
 137 #endif /* VRGROUP_4122 */
 138 #if defined VRGROUP_4181
 139 #define RTCINT_REG_W            VR4181_RTCINT_REG_W     /* RTC intr reg. */
 140 #endif /* VRGROUP_4181 */
 141 #endif /* defined SINGLE_VRIP_BASE */
 142
 143 #define         RTCINT_TCLOCK           (1<<3)  /* TClock */
 144 #define         RTCINT_RTCLONG2         (1<<2)  /* RTC Long 2 */
 145 #define         RTCINT_RTCLONG1         (1<<1)  /* RTC Long 1 */
 146 #define         RTCINT_ELAPSED          (1)     /* Elapsed time */
 147 #define         RTCINT_ALL              (RTCINT_TCLOCK|RTCINT_RTCLONG2|RTCINT_RTCLONG1|RTCINT_ELAPSED)
 148
 149 /* END rtcreg.h */