sys/arch/hpcmips/vr/vr4181dcureg.h

   1 /* $NetBSD: vr4181dcureg.h,v 1.1 2003/05/01 07:02:04 igy Exp $ */
   2
   3 /*
   4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Naoto Shimazaki of YOKOGAWA Electric Corporation.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  *      VR4181 DCU (DMA Control Unit) Registers definitions.
  34  *              dcu1 at 0x0a000020-0x0a000047
  35  *              dcu2 at 0x0a000650-0x0a000667
  36  *
  37  */
  38
  39 /* dcu1 registers */
  40 #define DCU_MICDEST1REG1_W      0x00    /* microphone destination 1 low */
  41 #define DCU_MICDEST1REG2_W      0x02    /* microphone destination 1 high */
  42 #define DCU_MICDEST2REG1_W      0x04    /* microphone destination 2 low */
  43 #define DCU_MICDEST2REG2_W      0x06    /* microphone destination 2 high */
  44 #define DCU_SPKRSRC1REG1_W      0x08    /* speaker destination 1 low */
  45 #define DCU_SPKRSRC1REG2_W      0x0a    /* speaker destination 1 high */
  46 #define DCU_SPKRSRC2REG1_W      0x0c    /* speaker destination 2 low */
  47 #define DCU_SPKRSRC2REG2_W      0x0e    /* speaker destination 2 high */
  48 #define DCU_DMARST_REG_W        0x20    /* DMA reset */
  49 #define  DCU_DMARST             0x0001  /* DMA reset */
  50 #define DCU_AIUDMAMSK_REG_W     0x26    /* audio DMA mask */
  51 #define  DCU_ENABLE_MIC         0x0008  /* enable microphone */
  52 #define  DCU_ENABLE_SPK         0x0004  /* enable speaker */
  53
  54 /* dcu2 registers */
  55 #define DCU_MICRCLEN_REG_W      0x08    /* microphone record length */
  56 #define DCU_SPKRCLEN_REG_W      0x0a    /* speaker record length */
  57 #define DCU_MICDMACFG_REG_W     0x0e    /* microphone DMA configuration */
  58 #define  DCU_MICLOAD            0x0100
  59 #define DCU_SPKDMACFG_REG_W     0x10    /* speaker DMA configuration */
  60 #define  DCU_SPKLOAD            0x0001
  61 #define DCU_DMAITRQ_REG_W       0x12    /* DMA interrupt request */
  62 #define  DCU_SPKEOP             0x20
  63 #define  DCU_MICEOP             0x10
  64 #define DCU_DMACTL_REG_W        0x14    /* DMA control */
  65 #define  DCU_SPKCNT_MSK         0xc000
  66 #define  DCU_SPKCNT_INC         0x0000
  67 #define  DCU_SPKCNT_DEC         0x4000
  68 #define  DCU_MICCNT_MSK         0x3000
  69 #define  DCU_MICCNT_INC         0x0000
  70 #define  DCU_MICCNT_DEC         0x1000
  71 #define DCU_DMAITMK_REG_W       0x16    /* DMA interrupt mask */
  72 #define  DCU_SPKEOP_ENABLE      0x0020
  73 #define  DCU_MICEOP_ENABLE      0x0010