sys/arch/hpcmips/vr/vripreg.h

   1 /*      $NetBSD: vripreg.h,v 1.7 2002/02/11 11:44:36 takemura Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1999
   5  *         Shin Takemura and PocketBSD Project. All rights reserved.
   6  * Copyright (c) 2001 SATO Kazumi, All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by the PocketBSD project
  19  *      and its contributors.
  20  * 4. Neither the name of the project nor the names of its contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGE.
  35  *
  36  */
  37
  38 #define VRIP_NO_ADDR            0x00000000
  39 /*
  40  * VR4181 registers
  41  */
  42 #define VR4181_BCU_ADDR         0x0a000000
  43 #define VR4181_DMAAU_ADDR       VRIP_NO_ADDR
  44 #define VR4181_DCU_ADDR         VRIP_NO_ADDR
  45 #define VR4181_CMU_ADDR         0x0a000004
  46 #define VR4181_ICU_ADDR         0x0a000080
  47 #define VR4181_PMU_ADDR         0x0a0000a0
  48 #define VR4181_RTC_ADDR         0x0a0000c0
  49 #define VR4181_DSU_ADDR         0x0a0000e0
  50 #define VR4181_GIU_ADDR         VRIP_NO_ADDR    /* XXX: no register */
  51 #define VR4181_PIU_ADDR         0x0a000122
  52 #define VR4181_AIU_ADDR         0x0a000160
  53 #define VR4181_KIU_ADDR         0x0a000180
  54 #define VR4181_DSIU_ADDR        0x0a0001a0
  55 #define VR4181_LED_ADDR         0x0a000240
  56 #define VR4181_SIU_ADDR         0x0c000010
  57 #define VR4181_HSP_ADDR         0x0a000020
  58 #define VR4181_FIR_ADDR         0x0a000000      /* XXX */
  59 #define VR4181_MEMCON_ADDR      0x0a000300
  60 #define VR4181_ISABRG_ADDR      0x0b0002c0
  61 #define VR4181_ECU_ADDR         0x0b0008e0
  62 #define VR4181_DCU81_ADDR       0x0a000020
  63 #define VR4181_CSI81_ADDR       0x0b000900
  64 #define VR4181_GIU81_ADDR       0x0b000300
  65 #define VR4181_LCD_ADDR         0x0a000400
  66 #define VR4181_SIU1_ADDR        0x0c000000
  67 #define VR4181_SCU_ARR          VRIP_NO_ADDR    /* XXX: no register */
  68 #define VR4181_SDRAMU_ADDR      VRIP_NO_ADDR    /* XXX: no register */
  69 #define VR4181_PCI_ADDR         VRIP_NO_ADDR    /* XXX: no register */
  70 #define VR4181_PCICONF_ADDR     VRIP_NO_ADDR    /* XXX: no register */
  71 #define VR4181_CSI_ADDR         VRIP_NO_ADDR    /* XXX: no register */
  72
  73 /*
  74  * VR4101-4121 registers
  75  */
  76 #define VR4102_BCU_ADDR         0x0b000000
  77 #define VR4102_DMAAU_ADDR       0x0b000020
  78 #define VR4102_DCU_ADDR         0x0b000040
  79 #define VR4102_CMU_ADDR         0x0b000060
  80 #define VR4102_ICU_ADDR         0x0b000080
  81 #define VR4102_PMU_ADDR         0x0b0000a0
  82 #define VR4102_RTC_ADDR         0x0b0000c0
  83 #define VR4102_DSU_ADDR         0x0b0000e0
  84 #define VR4102_GIU_ADDR         0x0b000100
  85 #define VR4102_PIU_ADDR         0x0b000120
  86 #define VR4102_AIU_ADDR         0x0b000160
  87 #define VR4102_KIU_ADDR         0x0b000180
  88 #define VR4102_DSIU_ADDR        0x0b0001a0
  89 #define VR4102_LED_ADDR         0x0b000240
  90 #define VR4102_SIU_ADDR         0x0c000000
  91 #define VR4102_HSP_ADDR         0x0c000020
  92 #define VR4102_FIR_ADDR         0x0b000000      /* XXX */
  93 #define VR4102_MEMCON_ADDR      VRIP_NO_ADDR    /* XXX: no register */
  94 #define VR4102_ISABRG_ADDR      VRIP_NO_ADDR    /* XXX: no register */
  95 #define VR4102_ECU_ADDR         VRIP_NO_ADDR    /* XXX: no register */
  96 #define VR4102_DCU81_ADDR       VRIP_NO_ADDR    /* XXX: no register */
  97 #define VR4102_CSI81_ADDR       VRIP_NO_ADDR    /* XXX: no register */
  98 #define VR4102_GIU81_ADDR       VRIP_NO_ADDR    /* XXX: no register */
  99 #define VR4102_SIU1_ADDR        VRIP_NO_ADDR    /* XXX: no register */
 100 #define VR4102_SCU_ARR          VRIP_NO_ADDR    /* XXX: no register */
 101 #define VR4102_SDRAMU_ADDR      VRIP_NO_ADDR    /* XXX: no register */
 102 #define VR4102_PCI_ADDR         VRIP_NO_ADDR    /* XXX: no register */
 103 #define VR4102_PCICONF_ADDR     VRIP_NO_ADDR    /* XXX: no register */
 104 #define VR4102_CSI_ADDR         VRIP_NO_ADDR    /* XXX: no register */
 105 /*
 106  * VR4122 registers
 107  */
 108 #define VR4122_BCU_ADDR         0x0f000000
 109 #define VR4122_DMAAU_ADDR       0x0f000020
 110 #define VR4122_DCU_ADDR         0x0f000040
 111 #define VR4122_CMU_ADDR         0x0f000060
 112 #define VR4122_ICU_ADDR         0x0f000080
 113 #define VR4122_PMU_ADDR         0x0f0000c0
 114 #define VR4122_RTC_ADDR         0x0f000100
 115 #define VR4122_DSU_ADDR         VRIP_NO_ADDR    /* XXX: no register */
 116 #define VR4122_GIU_ADDR         0x0f000140
 117 #define VR4122_PIU_ADDR         VRIP_NO_ADDR    /* XXX: no register */
 118 #define VR4122_AIU_ADDR         VRIP_NO_ADDR    /* XXX: no register */
 119 #define VR4122_KIU_ADDR         VRIP_NO_ADDR    /* XXX: no register */
 120 #define VR4122_DSIU_ADDR        0x0f000820
 121 #define VR4122_LED_ADDR         0x0f000180
 122 #define VR4122_SIU_ADDR         0x0f000800
 123 #define VR4122_HSP_ADDR         VRIP_NO_ADDR    /* XXX: no register */
 124 #define VR4122_FIR_ADDR         0x0f000840      /* XXX */
 125 #define VR4122_MEMCON_ADDR      VRIP_NO_ADDR    /* XXX: no register */
 126 #define VR4122_ISABRG_ADDR      VRIP_NO_ADDR    /* XXX: no register */
 127 #define VR4122_ECU_ADDR         VRIP_NO_ADDR    /* XXX: no register */
 128 #define VR4122_DCU81_ADDR       VRIP_NO_ADDR    /* XXX: no register */
 129 #define VR4122_CSI81_ADDR       VRIP_NO_ADDR    /* XXX: no register */
 130 #define VR4122_GIU81_ADDR       VRIP_NO_ADDR    /* XXX: no register */
 131 #define VR4122_SIU1_ADDR        VRIP_NO_ADDR    /* XXX: no register */
 132 #define VR4122_SCU_ARR          0x0f001000
 133 #define VR4122_SDRAMU_ADDR      0x0f000400
 134 #define VR4122_PCI_ADDR         0x0f000c00
 135 #define VR4122_PCICONF_ADDR     0x0f000d00
 136 #define VR4122_CSI_ADDR         0x0f0001a0
 137
 138 /*
 139  * VRIP base address
 140  *
 141  * REQUIRE: opt_vr41xx.h, vrcpudef.h
 142  */
 143 #include "opt_vr41xx.h"
 144 #include <hpcmips/vr/vrcpudef.h>
 145
 146 #if defined SINGLE_VRIP_BASE
 147
 148 #if defined VRGROUP_4181
 149 #define VRIP_BASE_ADDR          0x0a000000
 150
 151 #define VRIP_BCU_ADDR           VR4181_BCU_ADDR
 152 #define VRIP_DMAAU_ADDR         VR4181_DMAAU_ADDR
 153 #define VRIP_DCU_ADDR           VR4181_DCU_ADDR
 154 #define VRIP_CMU_ADDR           VR4181_CMU_ADDR
 155 #define VRIP_ICU_ADDR           VR4181_ICU_ADDR
 156 #define VRIP_PMU_ADDR           VR4181_PMU_ADDR
 157 #define VRIP_RTC_ADDR           VR4181_RTC_ADDR
 158 #define VRIP_DSU_ADDR           VR4181_DSU_ADDR
 159 #define VRIP_GIU_ADDR           VR4181_GIU_ADDR
 160 #define VRIP_PIU_ADDR           VR4181_PIU_ADDR
 161 #define VRIP_AIU_ADDR           VR4181_AIU_ADDR
 162 #define VRIP_KIU_ADDR           VR4181_KIU_ADDR
 163 #define VRIP_DSIU_ADDR          VR4181_DSIU_ADDR
 164 #define VRIP_LED_ADDR           VR4181_LED_ADDR
 165 #define VRIP_SIU_ADDR           VR4181_SIU_ADDR
 166 #define VRIP_HSP_ADDR           VR4181_HSP_ADDR
 167 #define VRIP_FIR_ADDR           VR4181_FIR_ADDR
 168 #define VRIP_MEMCON_ADDR        VR4181_MEMCON_ADDR
 169 #define VRIP_ISABRG_ADDR        VR4181_ISABRG_ADDR
 170 #define VRIP_ECU_ADDR           VR4181_ECU_ADDR
 171 #define VRIP_DCU81_ADDR         VR4181_DCU81_ADDR
 172 #define VRIP_CSI81_ADDR         VR4181_CSI81_ADDR
 173 #define VRIP_GIU81_ADDR         VR4181_GIU81_ADDR
 174 #define VRIP_LCD_ADDR           VR4181_LCD_ADDR
 175 #define VRIP_SIU1_ADDR          VR4181_SIU1_ADDR
 176 #define VRIP_SCU_ARR            VR4181_SCU_ARR          /* XXX: no register */
 177 #define VRIP_SDRAMU_ADDR        VR4181_SDRAMU_ADDR      /* XXX: no register */
 178 #define VRIP_PCI_ADDR           VR4181_PCI_ADDR         /* XXX: no register */
 179 #define VRIP_PCICONF_ADDR       VR4181_PCICONF_ADDR     /* XXX: no register */
 180 #define VRIP_CSI_ADDR           VR4181_CSI_ADDR         /* XXX: no register */
 181
 182 #endif /* VRGROUP_4181 */
 183
 184 #if defined VRGROUP_4122_4131
 185 #define VRIP_BASE_ADDR          0x0f000000
 186
 187 #define VRIP_BCU_ADDR           VR4122_BCU_ADDR
 188 #define VRIP_DMAAU_ADDR         VR4122_DMAAU_ADDR
 189 #define VRIP_DCU_ADDR           VR4122_DCU_ADDR
 190 #define VRIP_CMU_ADDR           VR4122_CMU_ADDR
 191 #define VRIP_ICU_ADDR           VR4122_ICU_ADDR
 192 #define VRIP_PMU_ADDR           VR4122_PMU_ADDR
 193 #define VRIP_RTC_ADDR           VR4122_RTC_ADDR
 194 #define VRIP_DSU_ADDR           VR4122_DSU_ADDR
 195 #define VRIP_GIU_ADDR           VR4122_GIU_ADDR
 196 #define VRIP_PIU_ADDR           VR4122_PIU_ADDR
 197 #define VRIP_AIU_ADDR           VR4122_AIU_ADDR
 198 #define VRIP_KIU_ADDR           VR4122_KIU_ADDR
 199 #define VRIP_DSIU_ADDR          VR4122_DSIU_ADDR
 200 #define VRIP_LED_ADDR           VR4122_LED_ADDR
 201 #define VRIP_SIU_ADDR           VR4122_SIU_ADDR
 202 #define VRIP_HSP_ADDR           VR4122_HSP_ADDR
 203 #define VRIP_FIR_ADDR           VR4122_FIR_ADDR
 204 #define VRIP_MEMCON_ADDR        VR4122_MEMCON_ADDR      /* XXX: no register */
 205 #define VRIP_ISABRG_ADDR        VR4122_ISABRG_ADDR      /* XXX: no register */
 206 #define VRIP_ECU_ADDR           VR4122_ECU_ADDR         /* XXX: no register */
 207 #define VRIP_DCU81_ADDR         VR4122_DCU81_ADDR       /* XXX: no register */
 208 #define VRIP_CSI81_ADDR         VR4122_CSI81_ADDR       /* XXX: no register */
 209 #define VRIP_GIU81_ADDR         VR4122_CSI81_ADDR       /* XXX: no register */
 210 #define VRIP_SIU1_ADDR          VR4122_SIU1_ADDR        /* XXX: no register */
 211 #define VRIP_SCU_ARR            VR4122_SCU_ARR          /* XXX: no register */
 212 #define VRIP_SDRAMU_ADDR        VR4122_SDRAMU_ADDR      /* XXX: no register */
 213 #define VRIP_PCI_ADDR           VR4122_PCI_ADDR         /* XXX: no register */
 214 #define VRIP_PCICONF_ADDR       VR4122_PCICONF_ADDR     /* XXX: no register */
 215 #define VRIP_CSI_ADDR           VR4122_CSI_ADDR         /* XXX: no register */
 216
 217 #endif /* VRGROUP_4122_4131 */
 218
 219 #if defined VRGROUP_4102_4121
 220 #define VRIP_BASE_ADDR          0x0b000000
 221
 222 #define VRIP_BCU_ADDR           VR4102_BCU_ADDR
 223 #define VRIP_DMAAU_ADDR         VR4102_DMAAU_ADDR
 224 #define VRIP_DCU_ADDR           VR4102_DCU_ADDR
 225 #define VRIP_CMU_ADDR           VR4102_CMU_ADDR
 226 #define VRIP_ICU_ADDR           VR4102_ICU_ADDR
 227 #define VRIP_PMU_ADDR           VR4102_PMU_ADDR
 228 #define VRIP_RTC_ADDR           VR4102_RTC_ADDR
 229 #define VRIP_DSU_ADDR           VR4102_DSU_ADDR
 230 #define VRIP_GIU_ADDR           VR4102_GIU_ADDR
 231 #define VRIP_PIU_ADDR           VR4102_PIU_ADDR
 232 #define VRIP_AIU_ADDR           VR4102_AIU_ADDR
 233 #define VRIP_KIU_ADDR           VR4102_KIU_ADDR
 234 #define VRIP_DSIU_ADDR          VR4102_DSIU_ADDR
 235 #define VRIP_LED_ADDR           VR4102_LED_ADDR
 236 #define VRIP_SIU_ADDR           VR4102_SIU_ADDR
 237 #define VRIP_HSP_ADDR           VR4102_HSP_ADDR
 238 #define VRIP_FIR_ADDR           VR4102_FIR_ADDR
 239 #define VRIP_MEMCON_ADDR        VR4102_MEMCON_ADDR      /* XXX: no register */
 240 #define VRIP_ISABRG_ADDR        VR4102_ISABRG_ADDR      /* XXX: no register */
 241 #define VRIP_ECU_ADDR           VR4102_ECU_ADDR         /* XXX: no register */
 242 #define VRIP_DCU81_ADDR         VR4102_DCU81_ADDR       /* XXX: no register */
 243 #define VRIP_CSI81_ADDR         VR4102_CSI81_ADDR       /* XXX: no register */
 244 #define VRIP_GIU81_ADDR         VR4102_GIU81_ADDR       /* XXX: no register */
 245 #define VRIP_SIU1_ADDR          VR4102_SIU1_ADDR        /* XXX: no register */
 246 #define VRIP_SCU_ARR            VR4102_SCU_ARR          /* XXX: no register */
 247 #define VRIP_SDRAMU_ADDR        VR4102_SDRAMU_ADDR      /* XXX: no register */
 248 #define VRIP_PCI_ADDR           VR4102_PCI_ADDR         /* XXX: no register */
 249 #define VRIP_PCICONF_ADDR       VR4102_PCICONF_ADDR     /* XXX: no register */
 250 #define VRIP_CSI_ADDR           VR4102_CSI_ADDR         /* XXX: no register */
 251
 252 #endif /* VRGROUP_4102_4121 */
 253
 254 #endif /* SINGLE_VRIP_BASE */
 255
 256 /*
 257  * ICU interrupt level
 258  */
 259 /* reserved                     62-31 */
 260 #define VRIP_INTR_BCU           25
 261 #define VRIP_INTR_CSI           24
 262 #define VRIP_INTR_SCU           23
 263 #define VRIP_INTR_PCI           22
 264 #define VRIP_INTR_LCD           22      /* 4181 */
 265 #define VRIP_INTR_DSIU          21
 266 #define VRIP_INTR_DCU81         21      /* 4181 */
 267 #define VRIP_INTR_FIR           20
 268 #define VRIP_INTR_TCLK          19
 269 #define VRIP_INTR_CSI81         19      /* 4181 */
 270 #define VRIP_INTR_HSP           18
 271 #define VRIP_INTR_ECU           18      /* 4181 */
 272 #define VRIP_INTR_LED           17
 273 #define VRIP_INTR_RTCL2         16
 274 /* reserved                     15,14 */
 275 #define VRIP_INTR_DOZEPIU       13
 276 #define VRIP_INTR_CLKRUN        12
 277 #define VRIP_INTR_SOFT          11
 278 #define VRIP_INTR_WRBERR        10
 279 #define VRIP_INTR_SIU           9
 280 #define VRIP_INTR_GIU           8
 281 #define VRIP_INTR_KIU           7
 282 #define VRIP_INTR_AIU           6
 283 #define VRIP_INTR_PIU           5
 284 /* reserved                     4       VRC4171 use this ??? */
 285 #define VRIP_INTR_ETIMER        3
 286 #define VRIP_INTR_RTCL1         2
 287 #define VRIP_INTR_POWER         1
 288 #define VRIP_INTR_BAT           0