sys/arch/hpcmips/vr/vrpiureg.h

   1 /*      $NetBSD: vrpiureg.h,v 1.3 2002/03/10 10:13:32 takemura Exp $    */
   2
   3 /*
   4  * Copyright (c) 1999 Shin Takemura All rights reserved.
   5  * Copyright (c) 1999 PocketBSD Project. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  */
  29
  30 /*
  31  * PIU (Touch panel interface unit) register definitions
  32  */
  33
  34 #define PIUCNT_REG_W    0x002   /* PIU Control register                 */
  35 #define         PIUCNT_PENSTC           (1<<13)
  36 #define         PIUCNT_PADSTATE_MASK    (0x7<<10)
  37 #define         PIUCNT_PADSTATE_SHIFT   10
  38 #define         PIUCNT_PADSTATE_CmdScan                 (0x7<<10)
  39 #define         PIUCNT_PADSTATE_IntervalNextScan        (0x6<<10)
  40 #define         PIUCNT_PADSTATE_PenDataScan             (0x5<<10)
  41 #define         PIUCNT_PADSTATE_WaitPenTouch            (0x4<<10)
  42 #define         PIUCNT_PADSTATE_RFU                     (0x3<<10)
  43 #define         PIUCNT_PADSTATE_ADPortScan              (0x2<<10)
  44 #define         PIUCNT_PADSTATE_Standby                 (0x1<<10)
  45 #define         PIUCNT_PADSTATE_Disable                 (0x0<<10)
  46 #define         PIUCNT_PADATSTOP        (1<<9)
  47 #define         PIUCNT_PADATSTART       (1<<8)
  48 #define         PIUCNT_PADSCANSTOP      (1<<7)
  49 #define         PIUCNT_PADSCANSTART     (1<<6)
  50 #define         PIUCNT_PADSCANTYPE      (1<<5)
  51 #define         PIUCNT_PIUMODE_MASK     (0x3<<3)
  52 #define         PIUCNT_PIUMODE_ADCONVERTER      (0x1<<3)
  53 #define         PIUCNT_PIUMODE_COORDINATE       (0x0<<3)
  54 #define         PIUCNT_PIUSEQEN         (1<<2)
  55 #define         PIUCNT_PIUPWR           (1<<1)
  56 #define         PIUCNT_PADRST           (1<<0)
  57
  58 #define PIUINT_REG_W    0x004   /* PIU Interruptcause register          */
  59 #define         PIUINT_OVP              (1<<15)
  60 #define         PIUINT_PADCMDINTR       (1<<6)
  61 #define         PIUINT_PADADPINTR       (1<<5)
  62 #define         PIUINT_PADPAGE1INTR     (1<<4)
  63 #define         PIUINT_PADPAGE0INTR     (1<<3)
  64 #define         PIUINT_PADDLOSTINTR     (1<<2)
  65 #define         PIUINT_PENCHGINTR       (1<<0)
  66 #define         PIUINT_ALLINTR  (PIUINT_PADCMDINTR | \
  67                                  PIUINT_PADADPINTR | \
  68                                  PIUINT_PADPAGE1INTR | \
  69                                  PIUINT_PADPAGE0INTR | \
  70                                  PIUINT_PADDLOSTINTR | \
  71                                  PIUINT_PENCHGINTR)
  72
  73 #define PIUSIVL_REG_W   0x006   /* PIU Data sampling interval register  */
  74 #define         PIUSIVL_SCANINTVAL_MASK 0x7FF
  75 #define         PIUSIVL_SCANINTVAL_UNIT 30      /* 30 us */
  76
  77 #define PIUSTBL_REG_W   0x008   /* PIU A/D converter start delay register*/
  78 #define         PIUSTBL_STABLE_MASK     0x1F
  79 #define         PIUSTBL_STABLE_UNIT     30      /* 30 us */
  80
  81 #define PIUCMD_REG_W    0x00A   /* PIU A/D command register             */
  82 #define         PIUCMD_STABLEON         (1<<12)
  83 #define         PIUCMD_TPYEN_MASK       (3<<10)
  84 #define         PIUCMD_TPY1_INPUT       (0<<11)
  85 #define         PIUCMD_TPY1_OUTPUT      (1<<11)
  86 #define         PIUCMD_TPY0_INPUT       (0<<10)
  87 #define         PIUCMD_TPY0_OUTPUT      (1<<10)
  88 #define         PIUCMD_TPXEN_MASK       (3<<8)
  89 #define         PIUCMD_TPX1_INPUT       (0<<9)
  90 #define         PIUCMD_TPX1_OUTPUT      (1<<9)
  91 #define         PIUCMD_TPX0_INPUT       (0<<8)
  92 #define         PIUCMD_TPX0_OUTPUT      (1<<8)
  93 #define         PIUCMD_TPYD_MASK        (3<<6)
  94 #define         PIUCMD_TPY1_LOW         (0<<7)
  95 #define         PIUCMD_TPY1_HIGH        (1<<7)
  96 #define         PIUCMD_TPY0_LOW         (0<<6)
  97 #define         PIUCMD_TPY0_HIGH        (1<<6)
  98 #define         PIUCMD_TPXD_MASK        (3<<4)
  99 #define         PIUCMD_TPX1_LOW         (0<<5)
 100 #define         PIUCMD_TPX1_HIGH        (1<<5)
 101 #define         PIUCMD_TPX0_LOW         (0<<4)
 102 #define         PIUCMD_TPX0_HIGH        (1<<4)
 103 #define         PIUCMD_ADCMD_MASK       0xF
 104 #define         PIUCMD_STANBYREQ        0xF
 105 #define         PIUCMD_AUDIOIN          0x7
 106 #define         PIUCMD_ADIN2            0x6
 107 #define         PIUCMD_ADIN1            0x5
 108 #define         PIUCMD_ADIN0            0x4
 109 #define         PIUCMD_TPY1             0x3
 110 #define         PIUCMD_TPY0             0x2
 111 #define         PIUCMD_TPX1             0x1
 112 #define         PIUCMD_TPX0             0x0
 113
 114 #define PIUASCN_REG_W   0x010   /* PIU A/D port scan  register          */
 115 #define         PIUACN_TPPSCAN          (1<<1)
 116 #define         PIUACN_ADPSSTART        (1<<0)
 117
 118 #define PIUAMSK_REG_W   0x012   /* PIU A/D scan mask register           */
 119 #define         PIUAMSK_ADINM3          (1<<7)
 120 #define         PIUAMSK_AUDIOM          PIUAMSK_ADINM3
 121 #define         PIUAMSK_ADINM2          (1<<6)
 122 #define         PIUAMSK_ADINM1          (1<<5)
 123 #define         PIUAMSK_ADINM0          (1<<4)
 124 #define         PIUAMSK_ADINMALL        0x70
 125 #define         PIUAMSK_TPYM1           (1<<3)
 126 #define         PIUAMSK_TPYM0           (1<<2)
 127 #define         PIUAMSK_TPXM1           (1<<1)
 128 #define         PIUAMSK_TPXM0           (1<<0)
 129 #define         PIUAMSK_TPMALL          0xF0
 130
 131 #define PIUCIVL_REG_W   0x01E   /* PIU Check interval register          */
 132 #define         PIUCIVL_CHKINTVAL_MASK  0x7FF
 133
 134 #ifndef PIUB_REG_OFFSSET
 135 #define PIUB_REG_OFFSSET        0x180
 136 #endif
 137 #define PIUPB00_REG_W   (PIUB_REG_OFFSSET+0x00) /* PIU Page 0 Buffer 0 reg */
 138 #define PIUPB01_REG_W   (PIUB_REG_OFFSSET+0x02) /* PIU Page 0 Buffer 1 reg */
 139 #define PIUPB02_REG_W   (PIUB_REG_OFFSSET+0x04) /* PIU Page 0 Buffer 2 reg */
 140 #define PIUPB03_REG_W   (PIUB_REG_OFFSSET+0x06) /* PIU Page 0 Buffer 3 reg */
 141 #define PIUPB04_REG_W   (PIUB_REG_OFFSSET+0x1C) /* PIU Page 0 Buffer 4 reg */
 142 #define PIUPB10_REG_W   (PIUB_REG_OFFSSET+0x08) /* PIU Page 1 Buffer 0 reg */
 143 #define PIUPB11_REG_W   (PIUB_REG_OFFSSET+0x0A) /* PIU Page 1 Buffer 1 reg */
 144 #define PIUPB12_REG_W   (PIUB_REG_OFFSSET+0x0C) /* PIU Page 1 Buffer 2 reg */
 145 #define PIUPB13_REG_W   (PIUB_REG_OFFSSET+0x0E) /* PIU Page 1 Buffer 3 reg */
 146 #define PIUPB14_REG_W   (PIUB_REG_OFFSSET+0x1E) /* PIU Page 1 Buffer 4 reg */
 147 #define PIUPB(page, n)  (((n)<4) ? \
 148                          (PIUPB00_REG_W + (page) * 8 + (n) * 2) : \
 149                          (PIUPB04_REG_W + (page) * 2))
 150 #define PIUPB_VALID             (1<<15)
 151 #define PIUPB_PADDATA_MASK      0x3FF
 152 #define PIUPB_PADDATA_MAX       0x3FF
 153 #define VRC4173PIUPB_PADDATA_MASK       0xFFF
 154 #define VRC4173PIUPB_PADDATA_MAX        0xFFF
 155
 156 #define PIUAB0_REG_W    (PIUB_REG_OFFSSET+0x10) /* PIU A/D scan Buffer 0 reg */
 157 #define PIUAB1_REG_W    (PIUB_REG_OFFSSET+0x12) /* PIU A/D scan Buffer 1 reg */
 158 #define PIUAB2_REG_W    (PIUB_REG_OFFSSET+0x14) /* PIU A/D scan Buffer 2 reg */
 159 #define PIUAB3_REG_W    (PIUB_REG_OFFSSET+0x16) /* PIU A/D scan Buffer 3 reg */
 160 #define PIUAB(n)        (PIUAB0_REG_W+(n)*2)
 161 #define PIUAB_VALID             (1<<15)
 162 #define PIUAB_PADDATA_MASK      0x3FF
 163 #define VRC4173PIUAB_PADDATA_MASK       0xFFF