sys/arch/hpcmips/vr/vrpmureg.h

   1 /*      $NetBSD: vrpmureg.h,v 1.3 1999/12/13 06:53:01 sato Exp $        */
   2
   3 /*-
   4  * Copyright (c) 1999 SATO Kazumi. All rights reserved.
   5  * Copyright (c) 1999 PocketBSD Project. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by the PocketBSD project
  18  *      and its contributors.
  19  * 4. Neither the name of the project nor the names of its contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  */
  36
  37 /*
  38  *      PMU (Power Management Unit) Registers definitions.
  39  *              start 0xB0000A0 (??????)
  40  *              start 0xF0000C0 (vr4122)
  41  */
  42
  43 #define PMUINT_REG_W    0x000   /* PMU interrupt/Status Register */
  44
  45 #define         PMUINT_GPIO3            (1<<15)         /* GPIO3 */
  46 #define         PMUINT_GPIO2            (1<<14)         /* GPIO2 */
  47 #define         PMUINT_GPIO1            (1<<13)         /* GPIO1 */
  48 #define         PMUINT_GPIO0            (1<<12)         /* GPIO0 */
  49 #define         PMUINT_DCDST            (1<<10)         /* DCD#  */
  50 #define         PMUINT_RTC              (1<<9)          /* RTC Alarm */
  51 #define         PMUINT_BATT             (1<<8)          /* BATTERY LOW  */
  52 #define         PMUINT_TIMOUTRST        (1<<5)          /* HAL Timer Reset */
  53 #define         PMUINT_RTCRST           (1<<4)          /* RTC Reset */
  54 #define         PMUINT_RSTSWRST         (1<<3)          /* Reset SW */
  55 #define         PMUINT_DMSWRST          (1<<2)          /* Deadman's SW */
  56 #define         PMUINT_BATTINTR         (1<<1)          /* Low batt during
  57                                                            normal operation */
  58 #define         PMUINT_POWERSW          (1)             /* Power Switch */
  59
  60 #define         PMUINT_ALL              (PMUINT_GPIO3|PMUINT_GPIO2|\
  61                                          PMUINT_GPIO1|PMUINT_GPIO0|\
  62                                          PMUINT_DCDST|PMUINT_RTC|\
  63                                          PMUINT_BATT|PMUINT_TIMOUTRST|\
  64                                          PMUINT_RTCRST|PMUINT_RSTSWRST|\
  65                                          PMUINT_DMSWRST|PMUINT_BATTINTR|\
  66                                          PMUINT_POWERSW)
  67
  68 #define PMUCNT_REG_W    0x002   /* PMU Control Register */
  69
  70 #define         PMUCNT_GPIO3MASK        (1<<15)         /* GPIO3 MASK */
  71 #define         PMUCNT_GPIO3EN          (1<<15)         /* GPIO3 Enable */
  72 #define         PMUCNT_GPIO3DS          (0<<15)         /* GPIO3 Disable */
  73
  74 #define         PMUCNT_GPIO2MASK        (1<<14)         /* GPIO2 MASK */
  75 #define         PMUCNT_GPIO2EN          (1<<14)         /* GPIO2 Enable */
  76 #define         PMUCNT_GPIO2DS          (0<<14)         /* GPIO2 Disable */
  77
  78 #define         PMUCNT_GPIO1MASK        (1<<13)         /* GPIO1 MASK */
  79 #define         PMUCNT_GPIO1EN          (1<<13)         /* GPIO1 Enable */
  80 #define         PMUCNT_GPIO1DS          (0<<13)         /* GPIO1 Disable */
  81
  82 #define         PMUCNT_GPIO0MASK        (1<<12)         /* GPIO0 MASK */
  83 #define         PMUCNT_GPIO0EN          (1<<12)         /* GPIO0 Enable */
  84 #define         PMUCNT_GPIO0DS          (0<<12)         /* GPIO0 Disable */
  85
  86 #define         PMUCNT_GPIO3TRIG        (1<<11)         /* GPIO3 TRIG */
  87 #define         PMUCNT_GPIO3D           (1<<11)         /* GPIO3 Fall */
  88 #define         PMUCNT_GPIO3U           (0<<11)         /* GPIO3 Raise */
  89
  90 #define         PMUCNT_GPIO2TRIG        (1<<10)         /* GPIO2 TRIG */
  91 #define         PMUCNT_GPIO2D           (1<<10)         /* GPIO2 Fall */
  92 #define         PMUCNT_GPIO2U           (0<<10)         /* GPIO2 Raise */
  93
  94 #define         PMUCNT_GPIO1TRIG        (1<<9)          /* GPIO1 TRIG */
  95 #define         PMUCNT_GPIO1D           (1<<9)          /* GPIO1 Fall */
  96 #define         PMUCNT_GPIO1U           (0<<9)          /* GPIO1 Raise */
  97
  98 #define         PMUCNT_GPIO0TRIG        (1<<8)          /* GPIO0 TRIG */
  99 #define         PMUCNT_GPIO0D           (1<<8)          /* GPIO0 Fall */
 100 #define         PMUCNT_GPIO0U           (0<<8)          /* GPIO0 Raise */
 101
 102 #define         PMUCNT_HALTIMERRST      (1<<2)          /* HAL Timer Reset */
 103 #define         PMUCNT_ONE              (1<<1)          /* ALWAYS write 1 */
 104
 105
 106 #define PMUINT2_REG_W   0x004   /* PMU interrupt/Status Register 2 */
 107
 108 #define         PMUINT_GPIO12           (1<<15)         /* GPIO12 */
 109 #define         PMUINT_GPIO11           (1<<14)         /* GPIO11 */
 110 #define         PMUINT_GPIO10           (1<<13)         /* GPIO10 */
 111 #define         PMUINT_GPIO9            (1<<12)         /* GPIO9 */
 112
 113 #define         PMUINT2_ALL             (PMUINT_GPIO12|PMUINT_GPIO11|\
 114                                          PMUINT_GPIO10|PMUINT_GPIO9)
 115
 116 #define PMUCNT2_REG_W   0x006   /* PMU Control Register 2 */
 117 #define         PMUCNT_GPIO12MASK       (1<<15)         /* GPIO12 MASK */
 118 #define         PMUCNT_GPIO12EN         (1<<15)         /* GPIO12 Enable */
 119 #define         PMUCNT_GPIO12DS         (0<<15)         /* GPIO12 Disable */
 120
 121 #define         PMUCNT_GPIO11MASK       (1<<14)         /* GPIO11 MASK */
 122 #define         PMUCNT_GPIO11EN         (1<<14)         /* GPIO11 Enable */
 123 #define         PMUCNT_GPIO11DS         (0<<14)         /* GPIO11 Disable */
 124
 125 #define         PMUCNT_GPIO10MASK       (1<<13)         /* GPIO10 MASK */
 126 #define         PMUCNT_GPIO10EN         (1<<13)         /* GPIO10 Enable */
 127 #define         PMUCNT_GPIO10DS         (0<<13)         /* GPIO10 Disable */
 128
 129 #define         PMUCNT_GPIO9MASK        (1<<12)         /* GPIO9 MASK */
 130 #define         PMUCNT_GPIO9EN          (1<<12)         /* GPIO9 Enable */
 131 #define         PMUCNT_GPIO9DS          (0<<12)         /* GPIO9 Disable */
 132
 133 #define         PMUCNT_GPIO12TRIG       (1<<11)         /* GPIO12 TRIG */
 134 #define         PMUCNT_GPIO12D          (1<<11)         /* GPIO12 Fail */
 135 #define         PMUCNT_GPIO12U          (0<<11)         /* GPIO12 Raise */
 136
 137 #define         PMUCNT_GPIO11TRIG       (1<<10)         /* GPIO11 TRIG */
 138 #define         PMUCNT_GPIO11D          (1<<10)         /* GPIO11 Fail */
 139 #define         PMUCNT_GPIO11U          (0<<10)         /* GPIO11 Raise */
 140
 141 #define         PMUCNT_GPIO10TRIG       (1<<9)          /* GPIO10 TRIG */
 142 #define         PMUCNT_GPIO10D          (1<<9)          /* GPIO10 Fail */
 143 #define         PMUCNT_GPIO10U          (0<<9)          /* GPIO10 Raise */
 144
 145 #define         PMUCNT_GPIO9TRIG        (1<<8)          /* GPIO9 TRIG */
 146 #define         PMUCNT_GPIO9D           (1<<8)          /* GPIO9 Fail */
 147 #define         PMUCNT_GPIO9U           (0<<8)          /* GPIO9 Raise */
 148
 149
 150 #define PMUWAIT_REG_W   0x008   /* PMU Wait Control Register (>= vr4111) */
 151 #define         PMUWAIT_DEFAULT         0x2c00          /* 343.75ms */
 152
 153 #define PMUDIV_REG_W    0x00C   /* PMU Div Mode Register (>= vr4121) */
 154 #define PMUINTRCLKDIV_REG_W 0x00E /* PMU IntrClk Div Mode Register
 155                                      (= vr4122) */
 156
 157 /* END vrpmureg.h */