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[netbsd-mini2440.git] / sys / arch / hppa / include / frame.h
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1 /* $NetBSD: frame.h,v 1.8 2009/04/30 07:01:27 skrll Exp $ */
3 /* $OpenBSD: frame.h,v 1.11 1999/11/25 18:28:06 mickey Exp $ */
5 /*
6 * Copyright (c) 1999-2004 Michael Shalayeff
7 * All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
32 #ifndef _HPPA_FRAME_H_
33 #define _HPPA_FRAME_H_
36 * Call frame definitions
38 #define HPPA_FRAME_NARGS (12)
39 #define HPPA_FRAME_MAXARGS (HPPA_FRAME_NARGS * 4)
40 #define HPPA_FRAME_ARG(n) (-(32 + 4*((n) + 1)))
41 #define HPPA_FRAME_CARG(n,sp) ((register_t *)((sp) + HPPA_FRAME_ARG(n)))
42 #define HPPA_FRAME_SIZE (64)
43 #define HPPA_FRAME_PSP (-4)
44 #define HPPA_FRAME_EP (-8)
45 #define HPPA_FRAME_CLUP (-12)
46 #define HPPA_FRAME_SL (-16)
47 #define HPPA_FRAME_CRP (-20)
48 #define HPPA_FRAME_ERP (-24)
49 #define HPPA_FRAME_ESR4 (-28)
50 #define HPPA_FRAME_EDP (-32)
51 #define HPPA_FRAME_ROUND(x) \
52 ((((uintptr_t)x) + HPPA_FRAME_SIZE - 1) & ~(HPPA_FRAME_SIZE - 1))
55 * Macros to decode processor status word.
57 #define HPPA_PC_PRIV_MASK 3
58 #define HPPA_PC_PRIV_KERN 0
59 #define HPPA_PC_PRIV_USER 3
60 #define USERMODE(pc) ((((register_t)pc) & HPPA_PC_PRIV_MASK) != HPPA_PC_PRIV_KERN)
61 #define KERNMODE(pc) (((register_t)pc) & ~HPPA_PC_PRIV_MASK)
63 #ifndef __ASSEMBLER__
65 * the trapframe is divided into two parts:
66 * one is saved while we are in the physical mode (beginning of the trap),
67 * and should be kept as small as possible, since all the interrupts will
68 * be lost during this phase, also it must be 64-bytes aligned, per
69 * pa-risc stack conventions, and its dependencies in the code (;
70 * the other part is filled out when we are already in the virtual mode,
71 * are able to catch interrupts (they are kept pending) and perform
72 * other trap activities (like tlb misses).
74 struct trapframe {
75 /* the `physical' part of the trapframe */
76 u_int tf_t1; /* r22 */
77 u_int tf_t2; /* r21 */
78 u_int tf_sp; /* r30 */
79 u_int tf_t3; /* r20 */
80 u_int tf_iisq_head; /* cr17 */
81 u_int tf_iisq_tail;
82 u_int tf_iioq_head; /* cr18 */
83 u_int tf_iioq_tail;
84 u_int tf_eiem; /* cr15 */
85 u_int tf_ipsw; /* cr22 */
86 u_int tf_sr3;
87 u_int tf_pidr1; /* cr8 */
88 u_int tf_isr; /* cr20 */
89 u_int tf_ior; /* cr21 */
90 u_int tf_iir; /* cr19 */
91 u_int tf_flags;
93 /* here starts the `virtual' part */
94 u_int tf_sar; /* cr11 */
95 u_int tf_r1;
96 u_int tf_rp; /* r2 */
97 u_int tf_r3; /* frame pointer when -g */
98 u_int tf_r4;
99 u_int tf_r5;
100 u_int tf_r6;
101 u_int tf_r7;
102 u_int tf_r8;
103 u_int tf_r9;
104 u_int tf_r10;
105 u_int tf_r11;
106 u_int tf_r12;
107 u_int tf_r13;
108 u_int tf_r14;
109 u_int tf_r15;
110 u_int tf_r16;
111 u_int tf_r17;
112 u_int tf_r18;
113 u_int tf_t4; /* r19 */
114 u_int tf_arg3; /* r23 */
115 u_int tf_arg2; /* r24 */
116 u_int tf_arg1; /* r25 */
117 u_int tf_arg0; /* r26 */
118 u_int tf_dp; /* r27 */
119 u_int tf_ret0; /* r28 */
120 u_int tf_ret1; /* r29 */
121 u_int tf_r31;
122 u_int tf_sr0;
123 u_int tf_sr1;
124 u_int tf_sr2;
125 u_int tf_sr4;
126 u_int tf_sr5;
127 u_int tf_sr6;
128 u_int tf_sr7;
129 u_int tf_pidr2; /* cr9 */
130 u_int tf_pidr3; /* cr12 */
131 u_int tf_pidr4; /* cr13 */
132 u_int tf_rctr; /* cr0 */
133 u_int tf_ccr; /* cr10 */
134 u_int tf_eirr; /* cr23 - DDB */
135 u_int tf_vtop; /* cr25 - DDB */
136 u_int tf_cr28; /* - DDB */
137 u_int tf_cr30; /* uaddr */
139 u_int tf_pad[4]; /* pad to 256 bytes */
142 #endif /* !__ASSEMBLER__ */
144 #endif /* !_HPPA_FRAME_H_ */