sys/arch/luna68k/dev/sioreg.h

   1 /* $NetBSD: sioreg.h,v 1.1.30.3 2004/09/21 13:17:24 skrll Exp $ */
   2 /*
   3  * Copyright (c) 1992, 1993
   4  *      The Regents of the University of California.  All rights reserved.
   5  *
   6  * This code is derived from software contributed to Berkeley by
   7  * OMRON Corporation.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  *      @(#)sioreg.h    8.1 (Berkeley) 6/10/93
  34  */
  35
  36 /*
  37  * Copyright (c) 1992 OMRON Corporation.
  38  *
  39  * This code is derived from software contributed to Berkeley by
  40  * OMRON Corporation.
  41  *
  42  * Redistribution and use in source and binary forms, with or without
  43  * modification, are permitted provided that the following conditions
  44  * are met:
  45  * 1. Redistributions of source code must retain the above copyright
  46  *    notice, this list of conditions and the following disclaimer.
  47  * 2. Redistributions in binary form must reproduce the above copyright
  48  *    notice, this list of conditions and the following disclaimer in the
  49  *    documentation and/or other materials provided with the distribution.
  50  * 3. All advertising materials mentioning features or use of this software
  51  *    must display the following acknowledgement:
  52  *      This product includes software developed by the University of
  53  *      California, Berkeley and its contributors.
  54  * 4. Neither the name of the University nor the names of its contributors
  55  *    may be used to endorse or promote products derived from this software
  56  *    without specific prior written permission.
  57  *
  58  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  59  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  60  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  61  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  62  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  63  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  64  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  65  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  66  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  67  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  68  * SUCH DAMAGE.
  69  *
  70  *      @(#)sioreg.h    8.1 (Berkeley) 6/10/93
  71  */
  72
  73 #define WR0             0x00
  74 #define WR1             0x01
  75 #define WR2             0x02
  76 #define WR3             0x03
  77 #define WR4             0x04
  78 #define WR5             0x05
  79 #define WR6             0x06
  80 #define WR7             0x07
  81
  82 #define WR2A            WR2
  83 #define WR2B            (WR2|0x10)
  84
  85 #define RR0             0x08
  86 #define RR1             0x09
  87 #define RR2             0x0A
  88 #define RR3             0x0B
  89 #define RR4             0x0C
  90
  91 #define RR2A            RR2
  92 #define RR2B            (RR2|0x10)
  93
  94 #define WR0_NOP         0x00    /* No Operation */
  95 #define WR0_SNDABRT     0x08    /* Send Abort (HDLC) */
  96 #define WR0_RSTINT      0x10    /* Reset External/Status Interrupt */
  97 #define WR0_CHANRST     0x18    /* Channel Reset */
  98 #define WR0_INTNXT      0x20    /* Enable Interrupt on Next Receive Character */
  99 #define WR0_RSTPEND     0x28    /* Reset Transmitter Interrput/DMA Pending */
 100 #define WR0_ERRRST      0x30    /* Error Reset */
 101 #define WR0_ENDINTR     0x38    /* End of Interrupt */
 102
 103 #define WR1_ESENBL      0x01    /* External/Status Interrupt Enable */
 104 #define WR1_TXENBL      0x02    /* Tx Interrupt/DMA Enable */
 105 #define WR1_STATVEC     0x04    /* Status Affects Vector (Only Chan-B) */
 106 #define WR1_RXDSEBL     0x00    /* Rx Interrupt/DMA Disable */
 107 #define WR1_RXFIRST     0x08    /* Interrupt only First Character Received */
 108 #define WR1_RXALLS      0x10    /* Interrupt Every Characters Received (with Special Char.) */
 109 #define WR1_RXALL       0x18    /* Interrupt Every Characters Received (without Special Char.) */
 110
 111 #define WR2_INTR_0      0x00    /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */
 112 #define WR2_INTR_1      0x04    /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */
 113 #define WR2_VEC85_1     0x00    /* 8085 Vectored Mode - 1 */
 114 #define WR2_VEC85_2     0x08    /* 8085 Vectored Mode - 2 */
 115 #define WR2_VEC86       0x10    /* 8086 Vectored */
 116 #define WR2_VEC85_3     0x18    /* 8085 Vectored Mode - 3 */
 117
 118 #define WR3_RXENBL      0x01    /* Rx Enable */
 119 #define WR3_RXCRC       0x08    /* Rx CRC Check */
 120 #define WR3_AUTOEBL     0x20    /* Auto Enable (flow control for MODEM) */
 121 #define WR3_RX5BIT      0x00    /* Rx Bits/Character: 5 Bits */
 122 #define WR3_RX7BIT      0x40    /* Rx Bits/Character: 7 Bits */
 123 #define WR3_RX6BIT      0x80    /* Rx Bits/Character: 6 Bits */
 124 #define WR3_RX8BIT      0xc0    /* Rx Bits/Character: 8 Bits */
 125
 126 #define WR4_NPARITY     0x00    /* No Parity */
 127 #define WR4_PARENAB     0x01    /* Parity Enable */
 128 #define WR4_OPARITY     0x01    /* Parity Odd */
 129 #define WR4_EPARITY     0x02    /* Parity Even */
 130 #define WR4_STOP1       0x04    /* Stop  Bits (1bit) */
 131 #define WR4_STOP15      0x08    /* Stop  Bits (1.5bit) */
 132 #define WR4_STOP2       0x0c    /* Stop  Bits (2bit) */
 133 #define WR4_BAUD96      0x40    /* Clock Rate (9600 BAUD) */
 134 #define WR4_BAUD48      0x80    /* Clock Rate (4800 BAUD) */
 135 #define WR4_BAUD24      0xc0    /* Clock Rate (2400 BAUD) */
 136
 137 #define WR5_TXCRC       0x01    /* Tx CRC Check */
 138 #define WR5_RTS         0x02    /* Request To Send     [RTS] */
 139 #define WR5_TXENBL      0x08    /* Transmit Enable */
 140 #define WR5_BREAK       0x10    /* Send Break          [BRK] */
 141 #define WR5_TX5BIT      0x00    /* Tx Bits/Character: 5 Bits */
 142 #define WR5_TX7BIT      0x20    /* Tx Bits/Character: 7 Bits */
 143 #define WR5_TX6BIT      0x40    /* Tx Bits/Character: 6 Bits */
 144 #define WR5_TX8BIT      0x60    /* Tx Bits/Character: 8 Bits */
 145 #define WR5_DTR         0x80    /* Data Terminal Ready [DTR] */
 146
 147 #define RR0_RXAVAIL     0x01    /* Rx Character Available */
 148 #define RR0_INTRPEND    0x02    /* Interrupt Pending (Channel-A Only) */
 149 #define RR0_TXEMPTY     0x04    /* Tx Buffer Empty */
 150 #define RR0_DCD         0x08    /* Data Carrier Detect [DCD] */
 151 #define RR0_SYNC        0x10    /* Synchronization */
 152 #define RR0_CTS         0x20    /* Clear To Send       [CTS] */
 153 #define RR0_BREAK       0x80    /* Break Detected      [BRK] */
 154
 155 #define RR1_PARITY      0x10    /* Parity Error */
 156 #define RR1_OVERRUN     0x20    /* Data Over Run */
 157 #define RR1_FRAMING     0x40    /* Framing Error */
 158
 159 #define RR_RXRDY        0x0100  /* Rx Character Available */
 160 #define RR_INTRPEND     0x0200  /* Interrupt Pending (Channel-A Only) */
 161 #define RR_TXRDY        0x0400  /* Tx Buffer Empty */
 162 #define RR_DCD          0x0800  /* Data Carrier Detect [DCD] */
 163 #define RR_SYNC         0x1000  /* Synchronization */
 164 #define RR_CTS          0x2000  /* Clear To Send       [CTS] */
 165 #define RR_BREAK        0x8000  /* Break Detected */
 166 #define RR_PARITY       0x0010  /* Parity Error */
 167 #define RR_OVERRUN      0x0020  /* Data Over Run */
 168 #define RR_FRAMING      0x0040  /* Framing Error */