sys/arch/luna68k/dev/timekeeper.h

   1 /* $NetBSD: timekeeper.h,v 1.1 2000/01/05 08:48:56 nisimura Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Tohru Nishimura.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Mostek MK48T02 for LUNA-1
  34  */
  35 #define MK_CSR          0       /* control register */
  36 #define MK_SEC          1       /* seconds (0..59; BCD) */
  37 #define MK_MIN          2       /* minutes (0..59; BCD) */
  38 #define MK_HOUR         3       /* hour (0..23; BCD) */
  39 #define MK_DOW          4       /* weekday (1..7) */
  40 #define MK_DOM          5       /* day in month (1..31; BCD) */
  41 #define MK_MONTH        6       /* month (1..12; BCD) */
  42 #define MK_YEAR         7       /* year (0..99; BCD) */
  43 /* bits in cl_csr */
  44 #define MK_CSR_WRITE    0x80    /* want to write */
  45 #define MK_CSR_READ     0x40    /* want to read (freeze clock) */
  46
  47 /*
  48  * Dallas Semiconductor DS1287 -- mc146818 compatible, for LUNA-2
  49  */
  50 #define MC_SEC          0x0     /* Time of year: seconds (0-59) */
  51 #define MC_ASEC         0x1     /* Alarm: seconds */
  52 #define MC_MIN          0x2     /* Time of year: minutes (0-59) */
  53 #define MC_AMIN         0x3     /* Alarm: minutes */
  54 #define MC_HOUR         0x4     /* Time of year: hour (see above) */
  55 #define MC_AHOUR        0x5     /* Alarm: hour */
  56 #define MC_DOW          0x6     /* Time of year: day of week (1-7) */
  57 #define MC_DOM          0x7     /* Time of year: day of month (1-31) */
  58 #define MC_MONTH        0x8     /* Time of year: month (1-12) */
  59 #define MC_YEAR         0x9     /* Time of year: year in century (0-99) */
  60
  61 #define MC_REGA         0xa     /* Control register A */
  62 #define  MC_REGA_RSMASK 0x0f    /* Interrupt rate select mask (see below) */
  63 #define  MC_REGA_DVMASK 0x70    /* Divisor select mask (see below) */
  64 #define  MC_REGA_UIP    0x80    /* Update in progress; read only. */
  65
  66 #define MC_REGB         0xb     /* Control register B */
  67 #define  MC_REGB_DSE    0x01    /* Daylight Savings Enable */
  68 #define  MC_REGB_24HR   0x02    /* 24-hour mode (AM/PM mode when clear) */
  69 #define  MC_REGB_BINARY 0x04    /* Binary mode (BCD mode when clear) */
  70 #define  MC_REGB_SQWE   0x08    /* Square Wave Enable */
  71 #define  MC_REGB_UIE    0x10    /* Update End interrupt enable */
  72 #define  MC_REGB_AIE    0x20    /* Alarm interrupt enable */
  73 #define  MC_REGB_PIE    0x40    /* Periodic interrupt enable */
  74 #define  MC_REGB_SET    0x80    /* Allow time to be set; stops updates */
  75
  76 #define MC_REGC         0xc     /* Control register C */
  77 /*       MC_REGC_UNUSED 0x0f    UNUSED */
  78 #define  MC_REGC_UF     0x10    /* Update End interrupt flag */
  79 #define  MC_REGC_AF     0x20    /* Alarm interrupt flag */
  80 #define  MC_REGC_PF     0x40    /* Periodic interrupt flag */
  81 #define  MC_REGC_IRQF   0x80    /* Interrupt request pending flag */
  82
  83 #define MC_REGD         0xd     /* Control register D */
  84 /*       MC_REGD_UNUSED 0x7f    UNUSED */
  85 #define  MC_REGD_VRT    0x80    /* Valid RAM and Time bit */
  86
  87 #define MC_NREGS        0xe     /* 14 registers; CMOS follows */
  88 #define MC_NTODREGS     0xa     /* 10 of those regs are for TOD and alarm */