sys/arch/m68k/fpe/fpu_fmovecr.c

   1 /*      $NetBSD: fpu_fmovecr.c,v 1.11 2005/12/11 12:17:52 christos Exp $        */
   2
   3 /*
   4  * Copyright (c) 1995  Ken Nakata
   5  *      All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of the author nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  *      @(#)fpu_fmovecr.c       10/8/95
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __KERNEL_RCSID(0, "$NetBSD: fpu_fmovecr.c,v 1.11 2005/12/11 12:17:52 christos Exp $");
  36
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <machine/frame.h>
  40
  41 #include "fpu_emulate.h"
  42
  43 /* XXX: quick consistency check */
  44 #if (FP_1 != 0x40000)
  45 Error you have to change this table when changing the mantissa size
  46 #endif
  47
  48 static struct fpn constrom[] = {
  49     /* fp_class, fp_sign, fp_exp, fp_sticky, fp_mant[0] ... [2] */
  50     { FPC_NUM, 0, 1, 0, { 0x6487e, 0xd5110b46, 0x11a80000 } },
  51     { FPC_NUM, 0, -2, 0, { 0x4d104, 0xd427de7f, 0xbcc00000 } },
  52     { FPC_NUM, 0, 1, 0, { 0x56fc2, 0xa2c515da, 0x54d00000 } },
  53     { FPC_NUM, 0, 0, 0, { 0x5c551, 0xd94ae0bf, 0x85e00000 } },
  54     { FPC_NUM, 0, -2, 0, { 0x6f2de, 0xc549b943, 0x8ca80000 } },
  55     { FPC_ZERO, 0, 0, 0, { 0x0, 0x0, 0x0 } },
  56     { FPC_NUM, 0, -1, 0, { 0x58b90, 0xbfbe8e7b, 0xcd600000 } },
  57     { FPC_NUM, 0, 1, 0, { 0x49aec, 0x6eed5545, 0x60b80000 } },
  58     { FPC_NUM, 0, 0, 0, { 0x40000, 0x0, 0x0 } },
  59     { FPC_NUM, 0, 3, 0, { 0x50000, 0x0, 0x0 } },
  60     { FPC_NUM, 0, 6, 0, { 0x64000, 0x0, 0x0 } },
  61     { FPC_NUM, 0, 13, 0, { 0x4e200, 0x0, 0x0 } },
  62     { FPC_NUM, 0, 26, 0, { 0x5f5e1, 0x0, 0x0 } },
  63     { FPC_NUM, 0, 53, 0, { 0x470de, 0x4df82000, 0x0 } },
  64     { FPC_NUM, 0, 106, 0, { 0x4ee2d, 0x6d415b85, 0xacf00000 } },
  65     { FPC_NUM, 0, 212, 0, { 0x613c0, 0xfa4ffe7d, 0x36a80000 } },
  66     { FPC_NUM, 0, 425, 0, { 0x49dd2, 0x3e4c074c, 0x67000000 } },
  67     { FPC_NUM, 0, 850, 0, { 0x553f7, 0x5fdcefce, 0xf4700000 } },
  68     { FPC_NUM, 0, 1700, 0, { 0x718cd, 0x5753074, 0x8e380000 } },
  69     { FPC_NUM, 0, 3401, 0, { 0x64bb3, 0xac340ba8, 0x60b80000 } },
  70     { FPC_NUM, 0, 6803, 0, { 0x4f459, 0xdaee29ea, 0xef280000 } },
  71     { FPC_NUM, 0, 13606, 0, { 0x62302, 0x90145104, 0xbcd80000 } },
  72 };
  73
  74 struct fpn *
  75 fpu_const(struct fpn *fp, u_int offset)
  76 {
  77     struct fpn *r;
  78
  79 #ifdef DEBUG
  80     if (fp == NULL) {
  81         panic("fpu_const: NULL pointer passed");
  82     }
  83 #endif
  84     if (offset == 0) {
  85         r = &constrom[0];
  86     } else if (0xb <= offset && offset <= 0xe) {
  87         r = &constrom[offset - 0xb + 1];
  88     } else if (0x30 <= offset && offset <= 0x3f) {
  89         r = &constrom[offset - 0x30 + 6];
  90     } else {
  91         /* return 0.0 for anything else (incl. valid offset 0xf) */
  92         r = &constrom[5];
  93     }
  94
  95     CPYFPN(fp, r);
  96
  97     return fp;
  98 }
  99
 100 int
 101 fpu_emul_fmovecr(struct fpemu *fe, struct instruction *insn)
 102 {
 103     int dstreg, offset;
 104     u_int *fpreg;
 105
 106     dstreg = (insn->is_word1 >> 7) & 0x7;
 107     offset = insn->is_word1 & 0x7F;
 108     fpreg = &(fe->fe_fpframe->fpf_regs[0]);
 109
 110     (void)fpu_const(&fe->fe_f3, offset);
 111     (void)fpu_upd_fpsr(fe, &fe->fe_f3);
 112     fpu_implode(fe, &fe->fe_f3, FTYPE_EXT, &fpreg[dstreg * 3]);
 113 #if DEBUG_FPE
 114     printf("  fpu_emul_fmovecr: result %08x,%08x,%08x to FP%d\n",
 115            fpreg[dstreg * 3], fpreg[dstreg * 3 + 1], fpreg[dstreg * 3 + 2],
 116            dstreg);
 117 #endif
 118     return 0;
 119 }