sys/arch/m68k/fpe/fpu_implode.c

   1 /*      $NetBSD: fpu_implode.c,v 1.10 2009/03/14 14:46:01 dsl Exp $ */
   2
   3 /*
   4  * Copyright (c) 1992, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This software was developed by the Computer Systems Engineering group
   8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
   9  * contributed to Berkeley.
  10  *
  11  * All advertising materials mentioning features or use of this software
  12  * must display the following acknowledgement:
  13  *      This product includes software developed by the University of
  14  *      California, Lawrence Berkeley Laboratory.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  * 3. Neither the name of the University nor the names of its contributors
  25  *    may be used to endorse or promote products derived from this software
  26  *    without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  *      @(#)fpu_implode.c       8.1 (Berkeley) 6/11/93
  41  */
  42
  43 /*
  44  * FPU subroutines: `implode' internal format numbers into the machine's
  45  * `packed binary' format.
  46  */
  47
  48 #include <sys/cdefs.h>
  49 __KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.10 2009/03/14 14:46:01 dsl Exp $");
  50
  51 #include <sys/types.h>
  52 #include <sys/systm.h>
  53
  54 #include <machine/ieee.h>
  55 #include <machine/reg.h>
  56
  57 #include "fpu_emulate.h"
  58 #include "fpu_arith.h"
  59
  60 /* Conversion from internal format -- note asymmetry. */
  61 static u_int    fpu_ftoi(struct fpemu *fe, struct fpn *fp);
  62 static u_int    fpu_ftos(struct fpemu *fe, struct fpn *fp);
  63 static u_int    fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *);
  64 static u_int    fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *);
  65
  66 /*
  67  * Round a number (algorithm from Motorola MC68882 manual, modified for
  68  * our internal format).  Set inexact exception if rounding is required.
  69  * Return true iff we rounded up.
  70  *
  71  * After rounding, we discard the guard and round bits by shifting right
  72  * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
  73  * This saves effort later.
  74  *
  75  * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
  76  * responsibility to fix this if necessary.
  77  */
  78 int
  79 fpu_round(register struct fpemu *fe, register struct fpn *fp)
  80 {
  81         register u_int m0, m1, m2;
  82         register int gr, s;
  83
  84         m0 = fp->fp_mant[0];
  85         m1 = fp->fp_mant[1];
  86         m2 = fp->fp_mant[2];
  87         gr = m2 & 3;
  88         s = fp->fp_sticky;
  89
  90         /* mant >>= FP_NG */
  91         m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
  92         m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
  93         m0 >>= FP_NG;
  94
  95         if ((gr | s) == 0)      /* result is exact: no rounding needed */
  96                 goto rounddown;
  97
  98         fe->fe_fpsr |= FPSR_INEX2;      /* inexact */
  99
 100         /* Go to rounddown to round down; break to round up. */
 101         switch (fe->fe_fpcr & FPCR_ROUND) {
 102
 103         case FPCR_NEAR:
 104         default:
 105                 /*
 106                  * Round only if guard is set (gr & 2).  If guard is set,
 107                  * but round & sticky both clear, then we want to round
 108                  * but have a tie, so round to even, i.e., add 1 iff odd.
 109                  */
 110                 if ((gr & 2) == 0)
 111                         goto rounddown;
 112                 if ((gr & 1) || fp->fp_sticky || (m2 & 1))
 113                         break;
 114                 goto rounddown;
 115
 116         case FPCR_ZERO:
 117                 /* Round towards zero, i.e., down. */
 118                 goto rounddown;
 119
 120         case FPCR_MINF:
 121                 /* Round towards -Inf: up if negative, down if positive. */
 122                 if (fp->fp_sign)
 123                         break;
 124                 goto rounddown;
 125
 126         case FPCR_PINF:
 127                 /* Round towards +Inf: up if positive, down otherwise. */
 128                 if (!fp->fp_sign)
 129                         break;
 130                 goto rounddown;
 131         }
 132
 133         /* Bump low bit of mantissa, with carry. */
 134         if (++m2 == 0 && ++m1 == 0)
 135                 m0++;
 136         fp->fp_sticky = 0;
 137         fp->fp_mant[0] = m0;
 138         fp->fp_mant[1] = m1;
 139         fp->fp_mant[2] = m2;
 140         return (1);
 141
 142 rounddown:
 143         fp->fp_sticky = 0;
 144         fp->fp_mant[0] = m0;
 145         fp->fp_mant[1] = m1;
 146         fp->fp_mant[2] = m2;
 147         return (0);
 148 }
 149
 150 /*
 151  * For overflow: return true if overflow is to go to +/-Inf, according
 152  * to the sign of the overflowing result.  If false, overflow is to go
 153  * to the largest magnitude value instead.
 154  */
 155 static int
 156 toinf(struct fpemu *fe, int sign)
 157 {
 158         int inf;
 159
 160         /* look at rounding direction */
 161         switch (fe->fe_fpcr & FPCR_ROUND) {
 162
 163         default:
 164         case FPCR_NEAR:         /* the nearest value is always Inf */
 165                 inf = 1;
 166                 break;
 167
 168         case FPCR_ZERO:         /* toward 0 => never towards Inf */
 169                 inf = 0;
 170                 break;
 171
 172         case FPCR_PINF:         /* toward +Inf iff positive */
 173                 inf = (sign == 0);
 174                 break;
 175
 176         case FPCR_MINF:         /* toward -Inf iff negative */
 177                 inf = sign;
 178                 break;
 179         }
 180         return (inf);
 181 }
 182
 183 /*
 184  * fpn -> int (int value returned as return value).
 185  *
 186  * N.B.: this conversion always rounds towards zero (this is a peculiarity
 187  * of the SPARC instruction set).
 188  */
 189 static u_int
 190 fpu_ftoi(struct fpemu *fe, register struct fpn *fp)
 191 {
 192         register u_int i;
 193         register int sign, exp;
 194
 195         sign = fp->fp_sign;
 196         switch (fp->fp_class) {
 197
 198         case FPC_ZERO:
 199                 return (0);
 200
 201         case FPC_NUM:
 202                 /*
 203                  * If exp >= 2^32, overflow.  Otherwise shift value right
 204                  * into last mantissa word (this will not exceed 0xffffffff),
 205                  * shifting any guard and round bits out into the sticky
 206                  * bit.  Then ``round'' towards zero, i.e., just set an
 207                  * inexact exception if sticky is set (see fpu_round()).
 208                  * If the result is > 0x80000000, or is positive and equals
 209                  * 0x80000000, overflow; otherwise the last fraction word
 210                  * is the result.
 211                  */
 212                 if ((exp = fp->fp_exp) >= 32)
 213                         break;
 214                 /* NB: the following includes exp < 0 cases */
 215                 if (fpu_shr(fp, FP_NMANT - 1 - FP_NG - exp) != 0)
 216                         /* m68881/2 do not underflow when
 217                            converting to integer */;
 218                 fpu_round(fe, fp);
 219                 i = fp->fp_mant[2];
 220                 if (i >= ((u_int)0x80000000 + sign))
 221                         break;
 222                 return (sign ? -i : i);
 223
 224         default:                /* Inf, qNaN, sNaN */
 225                 break;
 226         }
 227         /* overflow: replace any inexact exception with invalid */
 228         fe->fe_fpsr = (fe->fe_fpsr & ~FPSR_INEX2) | FPSR_OPERR;
 229         return (0x7fffffff + sign);
 230 }
 231
 232 /*
 233  * fpn -> single (32 bit single returned as return value).
 234  * We assume <= 29 bits in a single-precision fraction (1.f part).
 235  */
 236 static u_int
 237 fpu_ftos(struct fpemu *fe, register struct fpn *fp)
 238 {
 239         register u_int sign = fp->fp_sign << 31;
 240         register int exp;
 241
 242 #define SNG_EXP(e)      ((e) << SNG_FRACBITS)   /* makes e an exponent */
 243 #define SNG_MASK        (SNG_EXP(1) - 1)        /* mask for fraction */
 244
 245         /* Take care of non-numbers first. */
 246         if (ISNAN(fp)) {
 247                 /*
 248                  * Preserve upper bits of NaN, per SPARC V8 appendix N.
 249                  * Note that fp->fp_mant[0] has the quiet bit set,
 250                  * even if it is classified as a signalling NaN.
 251                  */
 252                 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
 253                 exp = SNG_EXP_INFNAN;
 254                 goto done;
 255         }
 256         if (ISINF(fp))
 257                 return (sign | SNG_EXP(SNG_EXP_INFNAN));
 258         if (ISZERO(fp))
 259                 return (sign);
 260
 261         /*
 262          * Normals (including subnormals).  Drop all the fraction bits
 263          * (including the explicit ``implied'' 1 bit) down into the
 264          * single-precision range.  If the number is subnormal, move
 265          * the ``implied'' 1 into the explicit range as well, and shift
 266          * right to introduce leading zeroes.  Rounding then acts
 267          * differently for normals and subnormals: the largest subnormal
 268          * may round to the smallest normal (1.0 x 2^minexp), or may
 269          * remain subnormal.  In the latter case, signal an underflow
 270          * if the result was inexact or if underflow traps are enabled.
 271          *
 272          * Rounding a normal, on the other hand, always produces another
 273          * normal (although either way the result might be too big for
 274          * single precision, and cause an overflow).  If rounding a
 275          * normal produces 2.0 in the fraction, we need not adjust that
 276          * fraction at all, since both 1.0 and 2.0 are zero under the
 277          * fraction mask.
 278          *
 279          * Note that the guard and round bits vanish from the number after
 280          * rounding.
 281          */
 282         if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) {   /* subnormal */
 283                 fe->fe_fpsr |= FPSR_UNFL;
 284                 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
 285                 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
 286                 if (fpu_round(fe, fp) && fp->fp_mant[2] == SNG_EXP(1))
 287                         return (sign | SNG_EXP(1) | 0);
 288                 if (fe->fe_fpsr & FPSR_INEX2)
 289                         fe->fe_fpsr |= FPSR_UNFL
 290                         /* mc68881/2 don't underflow when converting */;
 291                 return (sign | SNG_EXP(0) | fp->fp_mant[2]);
 292         }
 293         /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
 294         (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
 295 #ifdef DIAGNOSTIC
 296         if ((fp->fp_mant[2] & SNG_EXP(1 << FP_NG)) == 0)
 297                 panic("fpu_ftos");
 298 #endif
 299         if (fpu_round(fe, fp) && fp->fp_mant[2] == SNG_EXP(2))
 300                 exp++;
 301         if (exp >= SNG_EXP_INFNAN) {
 302                 /* overflow to inf or to max single */
 303                 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL;
 304                 if (toinf(fe, sign))
 305                         return (sign | SNG_EXP(SNG_EXP_INFNAN));
 306                 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
 307         }
 308 done:
 309         /* phew, made it */
 310         return (sign | SNG_EXP(exp) | (fp->fp_mant[2] & SNG_MASK));
 311 }
 312
 313 /*
 314  * fpn -> double (32 bit high-order result returned; 32-bit low order result
 315  * left in res[1]).  Assumes <= 61 bits in double precision fraction.
 316  *
 317  * This code mimics fpu_ftos; see it for comments.
 318  */
 319 static u_int
 320 fpu_ftod(struct fpemu *fe, register struct fpn *fp, u_int *res)
 321 {
 322         register u_int sign = fp->fp_sign << 31;
 323         register int exp;
 324
 325 #define DBL_EXP(e)      ((e) << (DBL_FRACBITS & 31))
 326 #define DBL_MASK        (DBL_EXP(1) - 1)
 327
 328         if (ISNAN(fp)) {
 329                 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
 330                 exp = DBL_EXP_INFNAN;
 331                 goto done;
 332         }
 333         if (ISINF(fp)) {
 334                 sign |= DBL_EXP(DBL_EXP_INFNAN);
 335                 res[1] = 0;
 336                 return (sign);
 337         }
 338         if (ISZERO(fp)) {
 339                 res[1] = 0;
 340                 return (sign);
 341         }
 342
 343         if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
 344                 fe->fe_fpsr |= FPSR_UNFL;
 345                 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
 346                 if (fpu_round(fe, fp) && fp->fp_mant[1] == DBL_EXP(1)) {
 347                         res[1] = 0;
 348                         return (sign | DBL_EXP(1) | 0);
 349                 }
 350                 if (fe->fe_fpsr & FPSR_INEX2)
 351                         fe->fe_fpsr |= FPSR_UNFL
 352                         /* mc68881/2 don't underflow when converting */;
 353                 exp = 0;
 354                 goto done;
 355         }
 356         (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
 357         if (fpu_round(fe, fp) && fp->fp_mant[1] == DBL_EXP(2))
 358                 exp++;
 359         if (exp >= DBL_EXP_INFNAN) {
 360                 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL;
 361                 if (toinf(fe, sign)) {
 362                         res[1] = 0;
 363                         return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
 364                 }
 365                 res[1] = ~0;
 366                 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
 367         }
 368 done:
 369         res[1] = fp->fp_mant[2];
 370         return (sign | DBL_EXP(exp) | (fp->fp_mant[1] & DBL_MASK));
 371 }
 372
 373 /*
 374  * fpn -> 68k extended (32 bit high-order result returned; two 32-bit low
 375  * order result left in res[1] & res[2]).  Assumes == 64 bits in extended
 376  * precision fraction.
 377  *
 378  * This code mimics fpu_ftos; see it for comments.
 379  */
 380 static u_int
 381 fpu_ftox(struct fpemu *fe, register struct fpn *fp, u_int *res)
 382 {
 383         register u_int sign = fp->fp_sign << 31;
 384         register int exp;
 385
 386 #define EXT_EXP(e)      ((e) << 16)
 387 /*
 388  * on m68k extended prec, significand does not share the same long
 389  * word with exponent
 390  */
 391 #define EXT_MASK        0
 392 #define EXT_EXPLICIT1   (1UL << (63 & 31))
 393 #define EXT_EXPLICIT2   (1UL << (64 & 31))
 394
 395         if (ISNAN(fp)) {
 396                 (void) fpu_shr(fp, FP_NMANT - EXT_FRACBITS);
 397                 exp = EXT_EXP_INFNAN;
 398                 goto done;
 399         }
 400         if (ISINF(fp)) {
 401                 sign |= EXT_EXP(EXT_EXP_INFNAN);
 402                 res[1] = res[2] = 0;
 403                 return (sign);
 404         }
 405         if (ISZERO(fp)) {
 406                 res[1] = res[2] = 0;
 407                 return (sign);
 408         }
 409
 410         if ((exp = fp->fp_exp + EXT_EXP_BIAS) < 0) {
 411                 fe->fe_fpsr |= FPSR_UNFL;
 412                 /* I'm not sure about this <=... exp==0 doesn't mean
 413                    it's a denormal in extended format */
 414                 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp);
 415                 if (fpu_round(fe, fp) && fp->fp_mant[1] == EXT_EXPLICIT1) {
 416                         res[1] = res[2] = 0;
 417                         return (sign | EXT_EXP(1) | 0);
 418                 }
 419                 if (fe->fe_fpsr & FPSR_INEX2)
 420                         fe->fe_fpsr |= FPSR_UNFL
 421                         /* mc68881/2 don't underflow */;
 422                 exp = 0;
 423                 goto done;
 424         }
 425 #if (FP_NMANT - FP_NG - EXT_FRACBITS) > 0
 426         (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS);
 427 #endif
 428         if (fpu_round(fe, fp) && fp->fp_mant[0] == EXT_EXPLICIT2)
 429                 exp++;
 430         if (exp >= EXT_EXP_INFNAN) {
 431                 fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL;
 432                 if (toinf(fe, sign)) {
 433                         res[1] = res[2] = 0;
 434                         return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0);
 435                 }
 436                 res[1] = res[2] = ~0;
 437                 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK);
 438         }
 439 done:
 440         res[1] = fp->fp_mant[1];
 441         res[2] = fp->fp_mant[2];
 442         return (sign | EXT_EXP(exp));
 443 }
 444
 445 /*
 446  * Implode an fpn, writing the result into the given space.
 447  */
 448 void
 449 fpu_implode(struct fpemu *fe, register struct fpn *fp, int type, register u_int *space)
 450 {
 451         /* XXX Dont delete exceptions set here: fe->fe_fpsr &= ~FPSR_EXCP; */
 452
 453         switch (type) {
 454         case FTYPE_LNG:
 455                 space[0] = fpu_ftoi(fe, fp);
 456                 break;
 457
 458         case FTYPE_SNG:
 459                 space[0] = fpu_ftos(fe, fp);
 460                 break;
 461
 462         case FTYPE_DBL:
 463                 space[0] = fpu_ftod(fe, fp, space);
 464                 break;
 465
 466         case FTYPE_EXT:
 467                 /* funky rounding precision options ?? */
 468                 space[0] = fpu_ftox(fe, fp, space);
 469                 break;
 470
 471         default:
 472                 panic("fpu_implode");
 473         }
 474 }