sys/arch/mips/adm5120/dev/ahcireg.h

   1 /* $NetBSD$ */
   2
   3 /*-
   4  * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or
   8  * without modification, are permitted provided that the following
   9  * conditions are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above
  13  *    copyright notice, this list of conditions and the following
  14  *    disclaimer in the documentation and/or other materials provided
  15  *    with the distribution.
  16  * 3. The names of the authors may not be used to endorse or promote
  17  *    products derived from this software without specific prior
  18  *    written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
  21  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  23  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
  25  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  27  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  29  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  30  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  31  * OF SUCH DAMAGE.
  32  */
  33 #ifndef _AHCIREG_H
  34 #define _AHCIREG_H
  35
  36 #define ADMHCD_REG_CONTROL              0x00
  37 #define ADMHCD_REG_INTSTATUS            0x04
  38 #define ADMHCD_REG_INTENABLE            0x08
  39 #define ADMHCD_REG_HOSTCONTROL          0x10
  40 #define ADMHCD_REG_FMINTERVAL           0x18
  41 #define ADMHCD_REG_FMNUMBER             0x1c
  42 #define ADMHCD_REG_LSTHRESH             0x70
  43 #define ADMHCD_REG_RHDESCR              0x74
  44 #define ADMHCD_REG_PORTSTATUS0          0x78
  45 #define ADMHCD_REG_PORTSTATUS1          0x7c
  46 #define ADMHCD_REG_HOSTHEAD             0x80
  47 #define ADMHCD_NUMPORTS         2
  48
  49 #define ADMHCD_HOST_EN          0x00000001      /* Host enable */
  50 #define ADMHCD_SW_INTREQ        0x00000002      /* request software int */
  51 #define ADMHCD_SW_RESET         0x00000008      /* Reset */
  52
  53 #define ADMHCD_INT_TD           0x00100000      /* TD completed */
  54 #define ADMHCD_INT_SW           0x20000000      /* software interrupt */
  55 #define ADMHCD_INT_FATAL        0x40000000      /* Fatal interrupt */
  56 #define ADMHCD_INT_ACT          0x80000000      /* Interrupt active */
  57
  58 #define ADMHCD_STATE_RST        0x00000000      /* bus state reset */
  59 #define ADMHCD_STATE_RES        0x00000001      /* bus state resume */
  60 #define ADMHCD_STATE_OP         0x00000002      /* bus state operational */
  61 #define ADMHCD_STATE_SUS        0x00000003      /* bus state suspended */
  62 #define ADMHCD_DMA_EN           0x00000004      /* enable dma engine */
  63
  64 #define ADMHCD_NPS              0x00000020      /* No Power Switch */
  65 #define ADMHCD_LPSC             0x04000000      /* Local power switch change */
  66
  67 #define ADMHCD_CCS              0x00000001      /* current connect status */
  68 #define ADMHCD_PES              0x00000002      /* port enable status */
  69 #define ADMHCD_PSS              0x00000004      /* port suspend status */
  70 #define ADMHCD_POCI             0x00000008      /* port overcurrent indicator */
  71 #define ADMHCD_PRS              0x00000010      /* port reset status */
  72 #define ADMHCD_PPS              0x00000100      /* port power status */
  73 #define ADMHCD_LSDA             0x00000200      /* low speed device attached */
  74 #define ADMHCD_CSC              0x00010000      /* connect status change */
  75 #define ADMHCD_PESC             0x00020000      /* enable status change */
  76 #define ADMHCD_PSSC             0x00040000      /* suspend status change */
  77 #define ADMHCD_OCIC             0x00080000      /* overcurrent change*/
  78 #define ADMHCD_PRSC             0x00100000      /* reset status change */
  79
  80 struct admhcd_ed {
  81         /* Don't change first four, they used for DMA */
  82         volatile u_int32_t                       control;
  83         volatile struct admhcd_td               *tail;
  84         volatile struct admhcd_td               *head;
  85         volatile struct admhcd_ed               *next;
  86         /* the rest is for the driver only: */
  87         u_int32_t                       unused[4];
  88 } __attribute__ ((packed));
  89
  90 #define ADMHCD_ED_EPSHIFT       7               /* Shift for endpoint number */
  91 #define ADMHCD_ED_INT           0x00000800      /* Is this an int endpoint */
  92 #define ADMHCD_ED_SPEED         0x00002000      /* Is it a high speed dev? */
  93 #define ADMHCD_ED_SKIP          0x00004000      /* Skip this ED */
  94 #define ADMHCD_ED_FORMAT        0x00008000      /* Is this an isoc endpoint */
  95 #define ADMHCD_ED_MAXSHIFT      16              /* Shift for max packet size */
  96
  97 struct admhcd_td {
  98         /* Don't change first four, they are used for DMA */
  99         volatile u_int32_t               control;
 100         volatile u_int32_t               buffer;
 101         volatile u_int32_t               buflen;
 102         volatile struct admhcd_td       *next;
 103         /* the rest is for the driver only: */
 104         /* struct urb           *urb;
 105         struct admhcd_td        *real; */
 106         u_int32_t                       len;
 107         u_int32_t                       unused[3];
 108 } __attribute__ ((packed));
 109
 110 #define ADMHCD_TD_OWN           0x80000000
 111 #define ADMHCD_TD_TOGGLE        0x00000000
 112 #define ADMHCD_TD_DATA0         0x01000000
 113 #define ADMHCD_TD_DATA1         0x01800000
 114 #define ADMHCD_TD_OUT           0x00200000
 115 #define ADMHCD_TD_IN            0x00400000
 116 #define ADMHCD_TD_SETUP         0x00000000
 117 #define ADMHCD_TD_ISO           0x00010000
 118 #define ADMHCD_TD_R             0x00040000
 119 #define ADMHCD_TD_INTEN         0x00010000
 120
 121 #define ADMHCD_TD_ERRMASK       0x78000000
 122 #define ADMHCD_TD_ERRSHIFT      27
 123
 124 #endif  /* _AHCIREG_H */