sys/arch/mips/alchemy/au_icu.c

   1 /*      $NetBSD: au_icu.c,v 1.24 2009/05/31 09:39:10 martin Exp $       */
   2
   3 /*-
   4  * Copyright (c) 2006 Itronix Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Garrett D'Amore for Itronix Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of Itronix Inc. may not be used to endorse
  18  *    or promote products derived from this software without specific
  19  *    prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*-
  35  * Copyright (c) 2001 The NetBSD Foundation, Inc.
  36  * All rights reserved.
  37  *
  38  * This code is derived from software contributed to The NetBSD Foundation
  39  * by Jason R. Thorpe.
  40  *
  41  * Redistribution and use in source and binary forms, with or without
  42  * modification, are permitted provided that the following conditions
  43  * are met:
  44  * 1. Redistributions of source code must retain the above copyright
  45  *    notice, this list of conditions and the following disclaimer.
  46  * 2. Redistributions in binary form must reproduce the above copyright
  47  *    notice, this list of conditions and the following disclaimer in the
  48  *    documentation and/or other materials provided with the distribution.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  51  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  52  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  53  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  54  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  55  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  56  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  57  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  58  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  59  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  60  * POSSIBILITY OF SUCH DAMAGE.
  61  */
  62
  63 /*
  64  * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs.
  65  *
  66  * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal
  67  * interrupt controllers.
  68  */
  69
  70 #include <sys/cdefs.h>
  71 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.24 2009/05/31 09:39:10 martin Exp $");
  72
  73 #include "opt_ddb.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/queue.h>
  77 #include <sys/malloc.h>
  78 #include <sys/systm.h>
  79 #include <sys/device.h>
  80 #include <sys/kernel.h>
  81
  82 #include <machine/bus.h>
  83 #include <machine/intr.h>
  84
  85 #include <mips/locore.h>
  86 #include <mips/alchemy/include/aureg.h>
  87 #include <mips/alchemy/include/auvar.h>
  88
  89 #define REGVAL(x)       *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
  90
  91 /*
  92  * This is a mask of bits to clear in the SR when we go to a
  93  * given hardware interrupt priority level.
  94  */
  95
  96 const uint32_t ipl_sr_bits[_IPL_N] = {
  97         0,                                      /*  0: IPL_NONE */
  98         MIPS_SOFT_INT_MASK_0,                   /*  1: IPL_SOFTCLOCK */
  99         MIPS_SOFT_INT_MASK_0,                   /*  2: IPL_SOFTNET */
 100         MIPS_SOFT_INT_MASK_0|
 101                 MIPS_SOFT_INT_MASK_1|
 102                 MIPS_INT_MASK_0|
 103                 MIPS_INT_MASK_1|
 104                 MIPS_INT_MASK_2|
 105                 MIPS_INT_MASK_3,                /*  3: IPL_VM */
 106         MIPS_SOFT_INT_MASK_0|
 107                 MIPS_SOFT_INT_MASK_1|
 108                 MIPS_INT_MASK_0|
 109                 MIPS_INT_MASK_1|
 110                 MIPS_INT_MASK_2|
 111                 MIPS_INT_MASK_3|
 112                 MIPS_INT_MASK_4|
 113                 MIPS_INT_MASK_5,                /*  4: IPL_{SCHED,HIGH} */
 114 };
 115
 116 #define NIRQS           64
 117
 118 struct au_icu_intrhead {
 119         struct evcnt intr_count;
 120         int intr_refcnt;
 121 };
 122 struct au_icu_intrhead au_icu_intrtab[NIRQS];
 123
 124 #define NINTRS                  4       /* MIPS INT0 - INT3 */
 125
 126 struct au_intrhand {
 127         LIST_ENTRY(au_intrhand) ih_q;
 128         int (*ih_func)(void *);
 129         void *ih_arg;
 130         int ih_irq;
 131         int ih_mask;
 132 };
 133
 134 struct au_cpuintr {
 135         LIST_HEAD(, au_intrhand) cintr_list;
 136         struct evcnt cintr_count;
 137 };
 138
 139 struct au_cpuintr au_cpuintrs[NINTRS];
 140 const char *au_cpuintrnames[NINTRS] = {
 141         "icu 0, req 0",
 142         "icu 0, req 1",
 143         "icu 1, req 0",
 144         "icu 1, req 1",
 145 };
 146
 147 static bus_addr_t ic0_base, ic1_base;
 148
 149 void
 150 au_intr_init(void)
 151 {
 152         int                     i;
 153         struct au_chipdep       *chip;
 154
 155         for (i = 0; i < NINTRS; i++) {
 156                 LIST_INIT(&au_cpuintrs[i].cintr_list);
 157                 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count,
 158                     EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]);
 159         }
 160
 161         chip = au_chipdep();
 162         KASSERT(chip != NULL);
 163
 164         ic0_base = chip->icus[0];
 165         ic1_base = chip->icus[1];
 166
 167         for (i = 0; i < NIRQS; i++) {
 168                 au_icu_intrtab[i].intr_refcnt = 0;
 169                 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count,
 170                     EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]);
 171         }
 172
 173         /* start with all interrupts masked */
 174         REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff;
 175         REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff;
 176         REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff;
 177         REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff;
 178         REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff;
 179         REGVAL(ic0_base + IC_TEST_BIT) = 0;
 180
 181         REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff;
 182         REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff;
 183         REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff;
 184         REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff;
 185         REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff;
 186         REGVAL(ic1_base + IC_TEST_BIT) = 0;
 187 }
 188
 189 void *
 190 au_intr_establish(int irq, int req, int level, int type,
 191     int (*func)(void *), void *arg)
 192 {
 193         struct au_intrhand      *ih;
 194         uint32_t                icu_base;
 195         int                     cpu_int, s;
 196         struct au_chipdep       *chip;
 197
 198         chip = au_chipdep();
 199         KASSERT(chip != NULL);
 200
 201         if (irq >= NIRQS)
 202                 panic("au_intr_establish: bogus IRQ %d", irq);
 203         if (req > 1)
 204                 panic("au_intr_establish: bogus request %d", req);
 205
 206         ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
 207         if (ih == NULL)
 208                 return (NULL);
 209
 210         ih->ih_func = func;
 211         ih->ih_arg = arg;
 212         ih->ih_irq = irq;
 213         ih->ih_mask = (1 << (irq & 31));
 214
 215         s = splhigh();
 216
 217         /*
 218          * First, link it into the tables.
 219          * XXX do we want a separate list (really, should only be one item, not
 220          *     a list anyway) per irq, not per CPU interrupt?
 221          */
 222         cpu_int = (irq < 32 ? 0 : 2) + req;
 223         LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q);
 224
 225         /*
 226          * Now enable it.
 227          */
 228         if (au_icu_intrtab[irq].intr_refcnt++ == 0) {
 229                 icu_base = (irq < 32) ? ic0_base : ic1_base;
 230
 231                 irq &= 31;      /* throw away high bit if set */
 232                 irq = 1 << irq; /* only used as a mask from here on */
 233
 234                 /* XXX Only level interrupts for now */
 235                 switch (type) {
 236                 case IST_NONE:
 237                 case IST_PULSE:
 238                 case IST_EDGE:
 239                         panic("unsupported irq type %d", type);
 240                         /* NOTREACHED */
 241                 case IST_LEVEL:
 242                 case IST_LEVEL_HIGH:
 243                         REGVAL(icu_base + IC_CONFIG2_SET) = irq;
 244                         REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
 245                         REGVAL(icu_base + IC_CONFIG0_SET) = irq;
 246                         break;
 247                 case IST_LEVEL_LOW:
 248                         REGVAL(icu_base + IC_CONFIG2_SET) = irq;
 249                         REGVAL(icu_base + IC_CONFIG1_SET) = irq;
 250                         REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
 251                         break;
 252                 }
 253                 wbflush();
 254
 255                 /* XXX handle GPIO interrupts - not done at all yet */
 256                 if (cpu_int & 0x1)
 257                         REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq;
 258                 else
 259                         REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq;
 260
 261                 /* Associate interrupt with peripheral */
 262                 REGVAL(icu_base + IC_SOURCE_SET) = irq;
 263
 264                 /* Actually enable the interrupt */
 265                 REGVAL(icu_base + IC_MASK_SET) = irq;
 266
 267                 /* And allow the interrupt to interrupt idle */
 268                 REGVAL(icu_base + IC_WAKEUP_SET) = irq;
 269
 270                 wbflush();
 271         }
 272         splx(s);
 273
 274         return (ih);
 275 }
 276
 277 void
 278 au_intr_disestablish(void *cookie)
 279 {
 280         struct au_intrhand *ih = cookie;
 281         uint32_t icu_base;
 282         int irq, s;
 283
 284         irq = ih->ih_irq;
 285
 286         s = splhigh();
 287
 288         /*
 289          * First, remove it from the table.
 290          */
 291         LIST_REMOVE(ih, ih_q);
 292
 293         /*
 294          * Now, disable it, if there is nothing remaining on the
 295          * list.
 296          */
 297         if (au_icu_intrtab[irq].intr_refcnt-- == 1) {
 298                 icu_base = (irq < 32) ? ic0_base : ic1_base;
 299
 300                 irq &= 31;      /* throw away high bit if set */
 301                 irq = 1 << irq; /* only used as a mask from here on */
 302
 303                 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq;
 304                 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
 305                 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
 306
 307                 /* disable with MASK_CLEAR and WAKEUP_CLEAR */
 308                 REGVAL(icu_base + IC_MASK_CLEAR) = irq;
 309                 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq;
 310                 wbflush();
 311         }
 312
 313         splx(s);
 314
 315         free(ih, M_DEVBUF);
 316 }
 317
 318 void
 319 au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
 320 {
 321         struct au_intrhand *ih;
 322         int level;
 323         uint32_t icu_base, irqstat, irqmask;
 324
 325         icu_base = irqstat = 0;
 326
 327         for (level = 3; level >= 0; level--) {
 328                 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
 329                         continue;
 330
 331                 /*
 332                  * XXX  the following may well be slow to execute.
 333                  *      investigate and possibly speed up.
 334                  *
 335                  * is something like:
 336                  *
 337                  *    irqstat = REGVAL(
 338                  *       (level & 4 == 0) ? IC0_BASE ? IC1_BASE +
 339                  *       (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT);
 340                  *
 341                  * be any better?
 342                  *
 343                  */
 344                 switch (level) {
 345                 case 0:
 346                         icu_base = ic0_base;
 347                         irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
 348                         break;
 349                 case 1:
 350                         icu_base = ic0_base;
 351                         irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
 352                         break;
 353                 case 2:
 354                         icu_base = ic1_base;
 355                         irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
 356                         break;
 357                 case 3:
 358                         icu_base = ic1_base;
 359                         irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
 360                         break;
 361                 }
 362                 irqmask = REGVAL(icu_base + IC_MASK_READ);
 363                 au_cpuintrs[level].cintr_count.ev_count++;
 364                 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) {
 365                         int mask = ih->ih_mask;
 366
 367                         if (mask & irqmask & irqstat) {
 368                                 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++;
 369                                 (*ih->ih_func)(ih->ih_arg);
 370
 371                                 if (REGVAL(icu_base + IC_MASK_READ) & mask) {
 372                                         REGVAL(icu_base + IC_MASK_CLEAR) = mask;
 373                                         REGVAL(icu_base + IC_MASK_SET) = mask;
 374                                         wbflush();
 375                                 }
 376                         }
 377                 }
 378                 cause &= ~(MIPS_INT_MASK_0 << level);
 379         }
 380
 381         /* Re-enable anything that we have processed. */
 382         _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
 383 }
 384
 385 /*
 386  * Some devices (e.g. PCMCIA) want to be able to mask interrupts at
 387  * the ICU, and leave them masked off until some later time
 388  * (e.g. reenabled by a soft interrupt).
 389  */
 390
 391 void
 392 au_intr_enable(int irq)
 393 {
 394         int             s;
 395         uint32_t        icu_base, mask;
 396
 397         if (irq >= NIRQS)
 398                 panic("au_intr_enable: bogus IRQ %d", irq);
 399
 400         icu_base = (irq < 32) ? ic0_base : ic1_base;
 401         mask = irq & 31;
 402         mask = 1 << mask;
 403
 404         s = splhigh();
 405         /* only enable the interrupt if we have a handler */
 406         if (au_icu_intrtab[irq].intr_refcnt) {
 407                 REGVAL(icu_base + IC_MASK_SET) = mask;
 408                 REGVAL(icu_base + IC_WAKEUP_SET) = mask;
 409                 wbflush();
 410         }
 411         splx(s);
 412 }
 413
 414 void
 415 au_intr_disable(int irq)
 416 {
 417         int             s;
 418         uint32_t        icu_base, mask;
 419
 420         if (irq >= NIRQS)
 421                 panic("au_intr_disable: bogus IRQ %d", irq);
 422
 423         icu_base = (irq < 32) ? ic0_base : ic1_base;
 424         mask = irq & 31;
 425         mask = 1 << mask;
 426
 427         s = splhigh();
 428         REGVAL(icu_base + IC_MASK_CLEAR) = mask;
 429         REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask;
 430         wbflush();
 431         splx(s);
 432 }