sys/arch/mips/alchemy/dev/aupscreg.h

   1 /* $NetBSD: aupscreg.h,v 1.2 2006/03/06 17:10:46 shige Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2006 Shigeyuki Fukushima.
   5  * All rights reserved.
   6  *
   7  * Written by Shigeyuki Fukushima.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above
  15  *    copyright notice, this list of conditions and the following
  16  *    disclaimer in the documentation and/or other materials provided
  17  *    with the distribution.
  18  * 3. The name of the author may not be used to endorse or promote
  19  *    products derived from this software without specific prior
  20  *    written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
  23  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  28  * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  31  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #ifndef _MIPS_ALCHEMY_DEV_AUPSCREG_H_
  36 #define _MIPS_ALCHEMY_DEV_AUPSCREG_H_
  37
  38 /*
  39  * PSC registers (offset from PSCn_BASE).
  40  */
  41
  42 /* psc_sel: PSC clock and protocol select
  43  *   CLK [5:4]
  44  *     00 = pscn_intclk (for SPI, SMBus, I2S Master[PSC3 Only])
  45  *     01 = PSCn_EXTCLK (for SPI, SMBus, I2S Master)
  46  *     10 = PSCn_CLK    (for AC97, I2S Slave)
  47  *     11 = Reserved
  48  *   PS [2:0]
  49  *     000 = Protocol disable
  50  *     001 = Reserved
  51  *     010 = SPI mode
  52  *     011 = I2S mode
  53  *     100 = AC97 mode
  54  *     101 = SMBus mode
  55  *     11x = Reserved
  56  */
  57 #define AUPSC_SEL                       0x00    /* R/W */
  58 #  define       AUPSC_SEL_CLK(x)        ((x & 0x03) << 4) /* CLK */
  59 #  define       AUPSC_SEL_PS(x)         (x & 0x07)
  60 #  define       AUPSC_SEL_DISABLE       0
  61 #  define       AUPSC_SEL_SPI           2
  62 #  define       AUPSC_SEL_I2S           3
  63 #  define       AUPSC_SEL_AC97          4
  64 #  define       AUPSC_SEL_SMBUS         5
  65
  66 /* psc_ctrl: PSC control
  67  *  ENA [1:0]
  68  *    00 = Disable/Reset
  69  *    01 = Reserved
  70  *    10 = Suspend
  71  *    11 = Enable
  72  */
  73 #define AUPSC_CTRL                      0x04    /* R/W */
  74 #  define       AUPSC_CTRL_ENA(x)       (x & 0x03)
  75 #  define       AUPSC_CTRL_DISABLE      0
  76 #  define       AUPSC_CTRL_SUSPEND      2
  77 #  define       AUPSC_CTRL_ENABLE       3
  78
  79 /* 0x0008 - 0x002F: Protocol-specific registers */
  80
  81 /* psc_stat: PSC status
  82  *  DI [1]
  83  *    1 = Device interrupt
  84  *  DR [1]
  85  *    1 = Device ready
  86  *  SR [0]
  87  *    1 = PSC ready
  88  *  all other bits a are protocol specific
  89  */
  90 #define AUPSC_STAT                      0x14
  91 #  define       AUPSC_STAT_SR           1
  92 #  define       AUPSC_STAT_DR           2
  93 #  define       AUPSC_STAT_DI           4
  94 /* PSC registers size */
  95 #define AUPSC_SIZE                      0x2f
  96
  97
  98 /*
  99  * SPI Protocol registers
 100  */
 101 #define AUPSC_SPICFG                    0x08    /* R/W */
 102 #define AUPSC_SPIMSK                    0x0c    /* R/W */
 103 #define AUPSC_SPIPCR                    0x10    /* R/W */
 104 #define AUPSC_SPISTAT                   0x14    /* Read only */
 105 #define AUPSC_SPIEVNT                   0x18    /* R/W */
 106 #define AUPSC_SPITXRX                   0x1c    /* R/W */
 107
 108 /*
 109  * I2S Protocol registers
 110  */
 111 #define AUPSC_I2SCFG                    0x08    /* R/W */
 112 #define AUPSC_I2SMSK                    0x0c    /* R/W */
 113 #define AUPSC_I2SPCR                    0x10    /* R/W */
 114 #define AUPSC_I2SSTAT                   0x14    /* Read only */
 115 #define AUPSC_I2SEVNT                   0x18    /* R/W */
 116 #define AUPSC_I2STXRX                   0x1c    /* R/W */
 117 #define AUPSC_I2SUDF                    0x20    /* R/W */
 118
 119 /*
 120  * AC97 Protocol registers
 121  */
 122 #define AUPSC_AC97CFG                   0x08    /* R/W */
 123 #define AUPSC_AC97MSK                   0x0c    /* R/W */
 124 #define AUPSC_AC97PCR                   0x10    /* R/W */
 125 #define AUPSC_AC97STAT                  0x14    /* Read only */
 126 #define AUPSC_AC97EVNT                  0x18    /* R/W */
 127 #define AUPSC_AC97TXRX                  0x1c    /* R/W */
 128 #define AUPSC_AC97CDC                   0x20    /* R/W */
 129 #define AUPSC_AC97RST                   0x24    /* R/W */
 130 #define AUPSC_AC97GPO                   0x28    /* R/W */
 131 #define AUPSC_AC97GPI                   0x2c    /* Read only */
 132
 133 /*
 134  * SMBus Protocol registers
 135  */
 136 #define AUPSC_SMBCFG                    0x08    /* R/W */
 137 #define AUPSC_SMBMSK                    0x0c    /* R/W */
 138 #define AUPSC_SMBPCR                    0x10    /* R/W */
 139 #define AUPSC_SMBSTAT                   0x14    /* Read only */
 140 #define AUPSC_SMBEVNT                   0x18    /* R/W */
 141 #define AUPSC_SMBTXRX                   0x1c    /* R/W */
 142 #define AUPSC_SMBTMR                    0x20    /* R/W */
 143
 144 #endif  /* _MIPS_ALCHEMY_DEV_AUPSCREG_H_ */