sys/arch/mips/alchemy/dev/if_aumacreg.h

   1 /* $NetBSD$ */
   2
   3 /*
   4  * Copyright (c) 2001 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _MIPS_ALCHEMY_DEV_AUMACREG_H_
  39 #define _MIPS_ALCHEMY_DEV_AUMACREG_H_
  40
  41 /*
  42  * Register description for the Alchemy Semiconductor Au1X00
  43  * Ethernet Media Access Controllers.
  44  */
  45
  46 #define MAC_BUFLEN       0x0800
  47 #define MAC_BUFLEN_JUMBO 0x2800
  48
  49 /*
  50  * MAC registers.
  51  */
  52
  53 #define MAC_CONTROL     0x0000  /* MAC control */
  54 #define CONTROL_RA      (1U << 31)      /* receive all */
  55 #define CONTROL_EM      (1U << 30)      /* 1 = big endian */
  56 #define CONTROL_DO      (1U << 23)      /* disable receive own */
  57 #define CONTROL_LM(x)   ((x) << 21)     /* loopback mode */
  58                                         /* 0 = normal */
  59                                         /* 1 = internal loopback */
  60                                         /* 2 = external loopback */
  61                                         /* 3 = reserved */
  62 #define CONTROL_F       (1U << 20)      /* full-duplex mode */
  63 #define CONTROL_PM      (1U << 19)      /* pass all multicast */
  64 #define CONTROL_PR      (1U << 18)      /* promiscuous mode */
  65 #define CONTROL_IF      (1U << 17)      /* inverse filtering */
  66 #define CONTROL_PB      (1U << 16)      /* pass bad frames */
  67 #define CONTROL_HO      (1U << 15)      /* hash-only filtering */
  68 #define CONTROL_HP      (1U << 13)      /* hash-perfect filtering */
  69 #define CONTROL_LC      (1U << 12)      /* re-tx on late collision */
  70 #define CONTROL_DB      (1U << 11)      /* disable broadcast frames */
  71 #define CONTROL_DR      (1U << 10)      /* disable retry */
  72 #define CONTROL_AP      (1U << 8)       /* automatic pad stripping */
  73 #define CONTROL_BL(x)   ((x) << 6)      /* backoff limit */
  74 #define CONTROL_DC      (1U << 5)       /* deferral check */
  75 #define CONTROL_TE      (1U << 3)       /* transmitter enable */
  76 #define CONTROL_RE      (1U << 2)       /* receiver enable */
  77
  78 #define MAC_ADDRHIGH    0x0004  /* high 16 bits of station address */
  79
  80 #define MAC_ADDRLOW     0x0008  /* low 32 bits of station address */
  81
  82 #define MAC_HASHHIGH    0x000c  /* high 32 bits of multicast hash */
  83
  84 #define MAC_HASHLOW     0x0010  /* low 32 bits of multicast hash */
  85
  86 #define MAC_MIICTRL     0x0014  /* MII PHY control */
  87 #define MIICTRL_PHYADDR(x) ((x) << 11)  /* PHY address */
  88 #define MIICTRL_MIIREG(x)  ((x) << 6)   /* MII register */
  89 #define MIICTRL_MW         (1U << 1)    /* MII write */
  90 #define MIICTRL_MB         (1U << 0)    /* MII busy */
  91
  92 #define MAC_MIIDATA     0x0018  /* MII PHY data */
  93 #define MIIDATA_MASK    0xffff          /* MII data bits */
  94
  95 #define MAC_FLOWCTRL    0x001c  /* control frame generation control */
  96 #define FLOWCTRL_PT(x)  ((x) << 16)     /* pause time */
  97 #define FLOWCTRL_PC     (1U << 2)       /* pass control frame */
  98 #define FLOWCTRL_FE     (1U << 1)       /* flow control enable */
  99 #define FLOWCTRL_FB     (1U << 0)       /* flow control busy */
 100
 101 #define MAC_VLAN1       0x0020  /* VLAN1 tag */
 102
 103 #define MAC_VLAN2       0x0024  /* VLAN2 tag */
 104
 105 /*
 106  * MAC Enable registers.
 107  */
 108
 109 #define MACEN_JP        (1U << 6)       /* jumbo packet enable */
 110 #define MACEN_E2        (1U << 5)       /* enable2 */
 111 #define MACEN_E1        (1U << 4)       /* enable1 */
 112 #define MACEN_C         (1U << 3)       /* 0 == coherent */
 113 #define MACEN_TS        (1U << 2)       /* disable toss */
 114 #define MACEN_E0        (1U << 1)       /* enable0 */
 115 #define MACEN_CE        (1U << 0)       /* clock enable */
 116
 117 /*
 118  * MAC DMA registers.
 119  */
 120
 121 #define MACDMA_TX_ENTRY(x)      ((x) << 4)
 122 #define MACDMA_RX_ENTRY(x)      (((x) << 4) + 0x100)
 123
 124 #define MACDMA_TX_STAT(x)       (MACDMA_TX_ENTRY(x) + 0x00)
 125 #define MACDMA_TX_ADDR(x)       (MACDMA_TX_ENTRY(x) + 0x04)
 126 #define MACDMA_TX_LEN(x)        (MACDMA_TX_ENTRY(x) + 0x08)
 127
 128 #define MACDMA_RX_STAT(x)       (MACDMA_RX_ENTRY(x) + 0x00)
 129 #define MACDMA_RX_ADDR(x)       (MACDMA_RX_ENTRY(x) + 0x04)
 130
 131 #define RX_STAT_MI      (1U << 31)      /* missed frame */
 132 #define RX_STAT_PF      (1U << 30)      /* packet filter pass */
 133 #define RX_STAT_FF      (1U << 29)      /* filtering fail */
 134 #define RX_STAT_BF      (1U << 28)      /* broadcast frame */
 135 #define RX_STAT_MF      (1U << 27)      /* multicast frame */
 136 #define RX_STAT_UC      (1U << 26)      /* unsupported control frame */
 137 #define RX_STAT_CF      (1U << 25)      /* control frame */
 138 #define RX_STAT_LE      (1U << 24)      /* length error */
 139 #define RX_STAT_V2      (1U << 23)      /* VLAN2 match */
 140 #define RX_STAT_V1      (1U << 22)      /* VLAN1 match */
 141 #define RX_STAT_CR      (1U << 21)      /* CRC error */
 142 #define RX_STAT_DB      (1U << 20)      /* dribbling bit */
 143 #define RX_STAT_ME      (1U << 19)      /* MII error */
 144 #define RX_STAT_FT      (1U << 18)      /* 0 = 802.3, 1 = Ethernet */
 145 #define RX_STAT_CS      (1U << 17)      /* collision seen */
 146 #define RX_STAT_FL      (1U << 16)      /* frame too long */
 147 #define RX_STAT_RF      (1U << 15)      /* runt frame */
 148 #define RX_STAT_WT      (1U << 14)      /* watchdog timeout */
 149 #define RX_STAT_L(x)    ((x) & 0x3fff)  /* frame length */
 150
 151 #define RX_STAT_ERRS    (RX_STAT_MI | RX_STAT_UC | RX_STAT_LE | RX_STAT_CR | \
 152                          RX_STAT_DB | RX_STAT_ME | RX_STAT_CS | RX_STAT_FL | \
 153                          RX_STAT_RF | RX_STAT_WT)
 154
 155 #define RX_ADDR_CB(x)   (((x) >> 2) & 3)/* current buffer */
 156 #define RX_ADDR_DN      (1U << 1)       /* transaction done */
 157 #define RX_ADDR_EN      (1U << 0)       /* enable this buffer */
 158
 159 #define TX_STAT_PR      (1U << 31)      /* packet retry */
 160 #define TX_STAT_CC(x)   (((x) >> 10) & 0xf) /* collision count */
 161 #define TX_STAT_LO      (1U << 9)       /* late collision observed */
 162 #define TX_STAT_DF      (1U << 8)       /* deferred transmission */
 163 #define TX_STAT_UR      (1U << 7)       /* data underrun */
 164 #define TX_STAT_EC      (1U << 6)       /* excessive collisions */
 165 #define TX_STAT_LC      (1U << 5)       /* late collision */
 166 #define TX_STAT_ED      (1U << 4)       /* excessive deferral */
 167 #define TX_STAT_LS      (1U << 3)       /* loss of carrier */
 168 #define TX_STAT_NC      (1U << 2)       /* no carrier */
 169 #define TX_STAT_JT      (1U << 1)       /* jabber timeout */
 170 #define TX_STAT_FA      (1U << 0)       /* frame aborted */
 171
 172 #define TX_ADDR_CB(x)   (((x) >> 2) & 3)/* current buffer */
 173 #define TX_ADDR_DN      (1U << 1)       /* transaction done */
 174 #define TX_ADDR_EN      (1U << 0)       /* enable this buffer */
 175
 176 #endif /* _MIPS_ALCHEMY_DEV_AUMACREG_H_ */