sys/arch/mips/alchemy/dev/usbdreg.h

   1 /* $NetBSD: aureg.h,v 1.9 2006/02/09 01:08:40 gdamore Exp $ */
   2
   3 /*
   4  * Copyright 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Simon Burge for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _MIPS_ALCHEMY_DEV_USBDREG_H
  39 #define _MIPS_ALCHEMY_DEV_USBDREG_H
  40
  41 #define USBD_EP0RD              0x00            /* Read from endpoint 0 */
  42 #define USBD_EP0WR              0x04            /* Write to endpoint 0 */
  43 #define USBD_EP1WR              0x08            /* Write to endpoint 1 */
  44 #define USBD_EP2WR              0x0c            /* Write to endpoint 2 */
  45 #define USBD_EP3RD              0x10            /* Read from endpoint 3 */
  46 #define USBD_EP4RD              0x14            /* Read from endpoint 4 */
  47 #define USBD_INTEN              0x18            /* Interrupt Enable Register */
  48 #define USBD_INTSTAT            0x1c            /* Interrupt Status Register */
  49 #define USBD_CONFIG             0x20            /* Write Configuration Register */
  50 #define USBD_EP0CS              0x24            /* Endpoint 0 control and status */
  51 #define USBD_EP1CS              0x28            /* Endpoint 1 control and status */
  52 #define USBD_EP2CS              0x2c            /* Endpoint 2 control and status */
  53 #define USBD_EP3CS              0x30            /* Endpoint 3 control and status */
  54 #define USBD_EP4CS              0x34            /* Endpoint 4 control and status */
  55 #define USBD_FRAMENUM           0x38            /* Current frame number */
  56 #define USBD_EP0RDSTAT          0x40            /* EP0 Read FIFO Status */
  57 #define USBD_EP0WRSTAT          0x44            /* EP0 Write FIFO Status */
  58 #define USBD_EP1WRSTAT          0x48            /* EP1 Write FIFO Status */
  59 #define USBD_EP2WRSTAT          0x4c            /* EP2 Write FIFO Status */
  60 #define USBD_EP3RDSTAT          0x50            /* EP3 Read FIFO Status */
  61 #define USBD_EP4RDSTAT          0x54            /* EP4 Read FIFO Status */
  62 #define USBD_ENABLE             0x58            /* USB Device Controller Enable */
  63
  64 #endif  /* _MIPS_ALCHEMY_DEV_USBDREG_H */