sys/arch/mips/include/cache_r5900.h

   1 /*      $NetBSD: cache_r5900.h,v 1.5 2005/12/24 20:07:19 perry Exp $    */
   2
   3 /*-
   4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #define CACHE_R5900_SIZE_I              16384
  33 #define CACHE_R5900_SIZE_D              8192
  34
  35 #define CACHE_R5900_LSIZE_I             64
  36 #define CACHE_R5900_LSIZE_D             64
  37
  38 #define CACHEOP_R5900_IINV_I            0x07    /* INDEX INVALIDATE */
  39 #define CACHEOP_R5900_HINV_I            0x0b    /* HIT INVALIDATE */
  40 #define CACHEOP_R5900_IWBINV_D          0x14
  41                                         /* INDEX WRITE BACK INVALIDATE */
  42 #define CACHEOP_R5900_ILTG_D            0x10    /* INDEX LOAD TAG */
  43 #define CACHEOP_R5900_ISTG_D            0x12    /* INDEX STORE TAG */
  44 #define CACHEOP_R5900_IINV_D            0x16    /* INDEX INVALIDATE */
  45 #define CACHEOP_R5900_HINV_D            0x1a    /* HIT INVALIDATE */
  46 #define CACHEOP_R5900_HWBINV_D          0x18    /* HIT WRITEBACK INVALIDATE */
  47 #define CACHEOP_R5900_ILDT_D            0x11    /* INDEX LOAD DATA */
  48 #define CACHEOP_R5900_ISDT_D            0x13    /* INDEX STORE DATA */
  49 #define CACHEOP_R5900_HWB_D             0x1c
  50                                         /* HIT WRITEBACK W/O INVALIDATE */
  51
  52 #if !defined(_LOCORE)
  53
  54 #define cache_op_r5900_line_64(va, op)                                  \
  55 do {                                                                    \
  56         __asm volatile(                                         \
  57                 ".set noreorder                                 \n\t"   \
  58                 "sync.l                                         \n\t"   \
  59                 "sync.p                                         \n\t"   \
  60                 "cache %1, 0(%0)                                \n\t"   \
  61                 "sync.l                                         \n\t"   \
  62                 "sync.p                                         \n\t"   \
  63                 ".set reorder"                                          \
  64             :                                                           \
  65             : "r" (va), "i" (op)                                        \
  66             : "memory");                                                \
  67 } while (/*CONSTCOND*/0)
  68
  69 #define cache_r5900_op_4lines_64(va, op)                                \
  70 do {                                                                    \
  71         __asm volatile(                                         \
  72                 ".set noreorder                                 \n\t"   \
  73                 "sync.l                                         \n\t"   \
  74                 "sync.p                                         \n\t"   \
  75                 "cache %1,   0(%0)                              \n\t"   \
  76                 "sync.l                                         \n\t"   \
  77                 "sync.p                                         \n\t"   \
  78                 "cache %1,  64(%0)                              \n\t"   \
  79                 "sync.l                                         \n\t"   \
  80                 "sync.p                                         \n\t"   \
  81                 "cache %1, 128(%0)                              \n\t"   \
  82                 "sync.l                                         \n\t"   \
  83                 "sync.p                                         \n\t"   \
  84                 "cache %1, 192(%0)                              \n\t"   \
  85                 "sync.l                                         \n\t"   \
  86                 "sync.p                                         \n\t"   \
  87                 ".set reorder"                                          \
  88             :                                                           \
  89             : "r" (va), "i" (op)                                        \
  90             : "memory");                                                \
  91 } while (/*CONSTCOND*/0)
  92
  93 #define cache_r5900_op_4lines_64_2way(va, op)                           \
  94 do {                                                                    \
  95         __asm volatile(                                         \
  96                 ".set noreorder                                 \n\t"   \
  97                 "sync.l                                         \n\t"   \
  98                 "sync.p                                         \n\t"   \
  99                 "cache %1,   0(%0)                              \n\t"   \
 100                 "sync.l                                         \n\t"   \
 101                 "sync.p                                         \n\t"   \
 102                 "cache %1,   1(%0)                              \n\t"   \
 103                 "sync.l                                         \n\t"   \
 104                 "sync.p                                         \n\t"   \
 105                 "cache %1,  64(%0)                              \n\t"   \
 106                 "sync.l                                         \n\t"   \
 107                 "sync.p                                         \n\t"   \
 108                 "cache %1,  65(%0)                              \n\t"   \
 109                 "sync.l                                         \n\t"   \
 110                 "sync.p                                         \n\t"   \
 111                 "cache %1, 128(%0)                              \n\t"   \
 112                 "sync.l                                         \n\t"   \
 113                 "sync.p                                         \n\t"   \
 114                 "cache %1, 129(%0)                              \n\t"   \
 115                 "sync.l                                         \n\t"   \
 116                 "sync.p                                         \n\t"   \
 117                 "cache %1, 192(%0)                              \n\t"   \
 118                 "sync.l                                         \n\t"   \
 119                 "sync.p                                         \n\t"   \
 120                 "cache %1, 193(%0)                              \n\t"   \
 121                 "sync.l                                         \n\t"   \
 122                 "sync.p                                         \n\t"   \
 123                 ".set reorder"                                          \
 124             :                                                           \
 125             : "r" (va), "i" (op)                                        \
 126             : "memory");                                                \
 127 } while (/*CONSTCOND*/0)
 128
 129 void    r5900_icache_sync_all_64(void);
 130 void    r5900_icache_sync_range_64(vaddr_t, vsize_t);
 131 void    r5900_icache_sync_range_index_64(vaddr_t, vsize_t);
 132
 133 void    r5900_pdcache_wbinv_all_64(void);
 134 void    r5900_pdcache_wbinv_range_64(vaddr_t, vsize_t);
 135 void    r5900_pdcache_wbinv_range_index_64(vaddr_t, vsize_t);
 136
 137 void    r5900_pdcache_inv_range_64(vaddr_t, vsize_t);
 138 void    r5900_pdcache_wb_range_64(vaddr_t, vsize_t);
 139
 140 #endif /* !_LOCORE */