sys/arch/mips/include/cache_tx39.h

   1 /*      $NetBSD: cache_tx39.h,v 1.5 2005/12/24 20:07:19 perry Exp $     */
   2
   3 /*-
   4  * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi; and by Jason R. Thorpe.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Cache definitions/operations for TX3900-style caches.
  34  *
  35  * XXX THIS IS NOT YET COMPLETE.
  36  */
  37
  38 #define CACHE_TX39_I                    0
  39 #define CACHE_TX39_D                    1
  40
  41 #define CACHEOP_TX3900_INDEX_INV        (0 << 2)        /* I */
  42 #define CACHEOP_TX3900_ILRUC            (1 << 2)        /* I, D */
  43 #define CACHEOP_TX3900_ILCKC            (2 << 2)        /* D */
  44 #define CACHEOP_TX3900_HIT_INV          (4 << 2)        /* D */
  45
  46 #define CACHEOP_TX3920_INDEX_INV        CACHEOP_TX3900_INDEX_INV
  47 #define CACHEOP_TX3920_INDEX_WB_INV     (0 << 2)        /* D */
  48 #define CACHEOP_TX3920_ILRUC            CACHEOP_TX3900_ILRUC
  49 #define CACHEOP_TX3920_INDEX_LOAD_TAG   (3 << 2)        /* I, D */
  50 #define CACHEOP_TX3920_HIT_INV          (4 << 2)        /* I, D */
  51 #define CACHEOP_TX3920_HIT_WB_INV       (5 << 2)        /* D */
  52 #define CACHEOP_TX3920_HIT_WB           (6 << 2)        /* D */
  53 #define CACHEOP_TX3920_ISTTAG           (7 << 2)        /* I, D */
  54
  55 #if !defined(_LOCORE)
  56
  57 /*
  58  * cache_tx39_op_line:
  59  *
  60  *      Perform the specified cache operation on a single line.
  61  */
  62 #define cache_op_tx39_line(va, op)                                      \
  63 do {                                                                    \
  64         __asm volatile(                                         \
  65                 ".set noreorder                                 \n\t"   \
  66                 ".set push                                      \n\t"   \
  67                 ".set mips3                                     \n\t"   \
  68                 "cache %1, 0(%0)                                \n\t"   \
  69                 ".set pop                                       \n\t"   \
  70                 ".set reorder"                                          \
  71             :                                                           \
  72             : "r" (va), "i" (op)                                        \
  73             : "memory");                                                \
  74 } while (/*CONSTCOND*/0)
  75
  76 /*
  77  * cache_tx39_op_32lines_4:
  78  *
  79  *      Perform the specified cache operation on 32 4-byte
  80  *      cache lines.
  81  */
  82 #define cache_tx39_op_32lines_4(va, op)                                 \
  83 do {                                                                    \
  84         __asm volatile(                                         \
  85                 ".set noreorder                                 \n\t"   \
  86                 ".set push                                      \n\t"   \
  87                 ".set mips3                                     \n\t"   \
  88                 "cache %1, 0x00(%0); cache %1, 0x04(%0);        \n\t"   \
  89                 "cache %1, 0x08(%0); cache %1, 0x0c(%0);        \n\t"   \
  90                 "cache %1, 0x10(%0); cache %1, 0x14(%0);        \n\t"   \
  91                 "cache %1, 0x18(%0); cache %1, 0x1c(%0);        \n\t"   \
  92                 "cache %1, 0x20(%0); cache %1, 0x24(%0);        \n\t"   \
  93                 "cache %1, 0x28(%0); cache %1, 0x2c(%0);        \n\t"   \
  94                 "cache %1, 0x30(%0); cache %1, 0x34(%0);        \n\t"   \
  95                 "cache %1, 0x38(%0); cache %1, 0x3c(%0);        \n\t"   \
  96                 "cache %1, 0x40(%0); cache %1, 0x44(%0);        \n\t"   \
  97                 "cache %1, 0x48(%0); cache %1, 0x4c(%0);        \n\t"   \
  98                 "cache %1, 0x50(%0); cache %1, 0x54(%0);        \n\t"   \
  99                 "cache %1, 0x58(%0); cache %1, 0x5c(%0);        \n\t"   \
 100                 "cache %1, 0x60(%0); cache %1, 0x64(%0);        \n\t"   \
 101                 "cache %1, 0x68(%0); cache %1, 0x6c(%0);        \n\t"   \
 102                 "cache %1, 0x70(%0); cache %1, 0x74(%0);        \n\t"   \
 103                 "cache %1, 0x78(%0); cache %1, 0x7c(%0);        \n\t"   \
 104                 ".set pop                                       \n\t"   \
 105                 ".set reorder"                                          \
 106             :                                                           \
 107             : "r" (va), "i" (op)                                        \
 108             : "memory");                                                \
 109 } while (/*CONSTCOND*/0)
 110
 111 /*
 112  * cache_tx39_op_32lines_16:
 113  *
 114  *      Perform the specified cache operation on 32 16-byte
 115  *      cache lines.
 116  */
 117 #define cache_tx39_op_32lines_16(va, op)                                \
 118 do {                                                                    \
 119         __asm volatile(                                         \
 120                 ".set noreorder                                 \n\t"   \
 121                 ".set push                                      \n\t"   \
 122                 ".set mips3                                     \n\t"   \
 123                 "cache %1, 0x000(%0); cache %1, 0x010(%0);      \n\t"   \
 124                 "cache %1, 0x020(%0); cache %1, 0x030(%0);      \n\t"   \
 125                 "cache %1, 0x040(%0); cache %1, 0x050(%0);      \n\t"   \
 126                 "cache %1, 0x060(%0); cache %1, 0x070(%0);      \n\t"   \
 127                 "cache %1, 0x080(%0); cache %1, 0x090(%0);      \n\t"   \
 128                 "cache %1, 0x0a0(%0); cache %1, 0x0b0(%0);      \n\t"   \
 129                 "cache %1, 0x0c0(%0); cache %1, 0x0d0(%0);      \n\t"   \
 130                 "cache %1, 0x0e0(%0); cache %1, 0x0f0(%0);      \n\t"   \
 131                 "cache %1, 0x100(%0); cache %1, 0x110(%0);      \n\t"   \
 132                 "cache %1, 0x120(%0); cache %1, 0x130(%0);      \n\t"   \
 133                 "cache %1, 0x140(%0); cache %1, 0x150(%0);      \n\t"   \
 134                 "cache %1, 0x160(%0); cache %1, 0x170(%0);      \n\t"   \
 135                 "cache %1, 0x180(%0); cache %1, 0x190(%0);      \n\t"   \
 136                 "cache %1, 0x1a0(%0); cache %1, 0x1b0(%0);      \n\t"   \
 137                 "cache %1, 0x1c0(%0); cache %1, 0x1d0(%0);      \n\t"   \
 138                 "cache %1, 0x1e0(%0); cache %1, 0x1f0(%0);      \n\t"   \
 139                 ".set pop                                       \n\t"   \
 140                 ".set reorder"                                          \
 141             :                                                           \
 142             : "r" (va), "i" (op)                                        \
 143             : "memory");                                                \
 144 } while (/*CONSTCOND*/0)
 145
 146 void    tx3900_icache_sync_all_16(void);
 147 void    tx3900_icache_sync_range_16(vaddr_t, vsize_t);
 148
 149 void    tx3900_pdcache_wbinv_all_4(void);
 150
 151 void    tx3900_pdcache_inv_range_4(vaddr_t, vsize_t);
 152 void    tx3900_pdcache_wb_range_4(vaddr_t, vsize_t);
 153
 154 void    tx3920_icache_sync_all_16wb(void);
 155 void    tx3920_icache_sync_range_16wt(vaddr_t, vsize_t);
 156 void    tx3920_icache_sync_range_16wb(vaddr_t, vsize_t);
 157
 158 void    tx3920_pdcache_wbinv_all_16wt(void);
 159 void    tx3920_pdcache_wbinv_all_16wb(void);
 160 void    tx3920_pdcache_wbinv_range_16wb(vaddr_t, vsize_t);
 161
 162 void    tx3920_pdcache_inv_range_16(vaddr_t, vsize_t);
 163 void    tx3920_pdcache_wb_range_16wt(vaddr_t, vsize_t);
 164 void    tx3920_pdcache_wb_range_16wb(vaddr_t, vsize_t);
 165
 166 void    tx3900_icache_do_inv_index_16(vaddr_t, vsize_t);
 167 void    tx3920_icache_do_inv_16(vaddr_t, vsize_t);
 168
 169 #endif /* !_LOCORE */