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[netbsd-mini2440.git] / sys / arch / mips / include / cpuregs.h
blob8a2cadb7a418d9bcbdee69689951e888e7822508
1 /* $NetBSD: cpuregs.h,v 1.76 2009/08/06 00:42:58 matt Exp $ */
2
3 /*
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
35 *
36 * machConst.h --
37 *
38 * Machine dependent constants.
39 *
40 * Copyright (C) 1989 Digital Equipment Corporation.
41 * Permission to use, copy, modify, and distribute this software and
42 * its documentation for any purpose and without fee is hereby granted,
43 * provided that the above copyright notice appears in all copies.
44 * Digital Equipment Corporation makes no representations about the
45 * suitability of this software for any purpose. It is provided "as is"
46 * without express or implied warranty.
47 *
48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
54 */
55
56 #ifndef _MIPS_CPUREGS_H_
57 #define _MIPS_CPUREGS_H_
58
59 #include <sys/cdefs.h> /* For __CONCAT() */
60
61 #if defined(_KERNEL_OPT)
62 #include "opt_cputype.h"
63 #endif
64
65 /*
66 * Address space.
67 * 32-bit mips CPUS partition their 32-bit address space into four segments:
68 *
69 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
70 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
71 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
72 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
73 *
74 * mips1 physical memory is limited to 512Mbytes, which is
75 * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
76 * Caching of mapped addresses is controlled by bits in the TLB entry.
77 */
78
79 #ifdef _LP64
80 #define MIPS_XUSEG_START (0L << 62)
81 #define MIPS_XUSEG_P(x) (((uint64_t)(x) >> 62) == 0)
82 #define MIPS_USEG_P(x) ((uintptr_t)(x) < 0x80000000L)
83 #define MIPS_XSSEG_START (1L << 62)
84 #define MIPS_XSSEG_P(x) (((uint64_t)(x) >> 62) == 1)
85 #endif
86
87 /*
88 * MIPS addresses are signed and we defining as negative so that
89 * in LP64 kern they get sign-extended correctly.
90 */
91 #ifndef _LOCORE
92 #define MIPS_KSEG0_START (-0x7fffffffL-1) /* 0x80000000 */
93 #define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */
94 #define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */
95 #define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */
96 #define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */
97 #endif
98
99 #define MIPS_PHYS_MASK 0x1fffffff
100
101 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
102 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START)
103 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
104 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START)
105
106 #define MIPS_KSEG0_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START)
107 #define MIPS_KSEG1_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START)
108 #define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x))
109
110 /* Map virtual address to index in mips3 r4k virtually-indexed cache */
111 #define MIPS3_VA_TO_CINDEX(x) \
112 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START)
113
114 #ifndef _LOCORE
115 #define MIPS_XSEG_MASK (0x3fffffffffffffffLL)
116 #define MIPS_XKSEG_START (0x3ULL << 62)
117 #define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3)
118
119 #define MIPS_XKPHYS_START (0x2ULL << 62)
120 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
121 (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x))
122 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
123 (mips3_xkphys_cached | (x))
124 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
125 (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x))
126 #define MIPS_XKPHYS_TO_PHYS(x) ((uint64_t)(x) & 0x07ffffffffffffffLL)
127 #define MIPS_XKPHYS_TO_CCA(x) (((uint64_t)(x) >> 59) & 7)
128 #define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2)
129 #endif /* _LOCORE */
130
131 #define CCA_UNCACHED 2
132 #define CCA_CACHEABLE 3 /* cacheable non-coherent */
133
134 /* CPU dependent mtc0 hazard hook */
135 #define COP0_SYNC /* nothing */
136 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
137
138 /*
139 * The bits in the cause register.
140 *
141 * Bits common to r3000 and r4000:
142 *
143 * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
144 * MIPS_CR_COP_ERR Coprocessor error.
145 * MIPS_CR_IP Interrupt pending bits defined below.
146 * (same meaning as in CAUSE register).
147 * MIPS_CR_EXC_CODE The exception type (see exception codes below).
148 *
149 * Differences:
150 * r3k has 4 bits of execption type, r4k has 5 bits.
151 */
152 #define MIPS_CR_BR_DELAY 0x80000000
153 #define MIPS_CR_COP_ERR 0x30000000
154 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
155 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
156 #define MIPS_CR_IP 0x0000FF00
157 #define MIPS_CR_EXC_CODE_SHIFT 2
158
159 /*
160 * The bits in the status register. All bits are active when set to 1.
161 *
162 * R3000 status register fields:
163 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
164 * MIPS_SR_TS TLB shutdown.
165 *
166 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
167 *
168 * Differences:
169 * r3k has cache control is via frobbing SR register bits, whereas the
170 * r4k cache control is via explicit instructions.
171 * r3k has a 3-entry stack of kernel/user bits, whereas the
172 * r4k has kernel/supervisor/user.
173 */
174 #define MIPS_SR_COP_USABILITY 0xf0000000
175 #define MIPS_SR_COP_0_BIT 0x10000000
176 #define MIPS_SR_COP_1_BIT 0x20000000
177
178 /* r4k and r3k differences, see below */
179
180 #define MIPS_SR_MX 0x01000000 /* MIPS64 */
181 #define MIPS_SR_PX 0x00800000 /* MIPS64 */
182 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
183 #define MIPS_SR_TS 0x00200000
184
185 /* r4k and r3k differences, see below */
186
187 #define MIPS_SR_INT_IE 0x00000001
188 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
189 /*#define MIPS_SR_INT_MASK 0x0000ff00*/
190
191
192 /*
193 * The R2000/R3000-specific status register bit definitions.
194 * all bits are active when set to 1.
195 *
196 * MIPS_SR_PARITY_ERR Parity error.
197 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
198 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
199 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
200 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
201 * Interrupt enable bits defined below.
202 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
203 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
204 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
205 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
206 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
207 */
208
209 #define MIPS1_PARITY_ERR 0x00100000
210 #define MIPS1_CACHE_MISS 0x00080000
211 #define MIPS1_PARITY_ZERO 0x00040000
212 #define MIPS1_SWAP_CACHES 0x00020000
213 #define MIPS1_ISOL_CACHES 0x00010000
214
215 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
216 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
217 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
218 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
219 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
220
221 /* backwards compatibility */
222 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
223 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
224 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
225 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
226 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
227
228 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
229 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
230 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
231 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
232 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
233
234 /*
235 * R4000 status register bit definitons,
236 * where different from r2000/r3000.
237 */
238 #define MIPS3_SR_XX 0x80000000
239 #define MIPS3_SR_RP 0x08000000
240 #define MIPS3_SR_FR 0x04000000
241 #define MIPS3_SR_RE 0x02000000
242
243 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
244 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
245 #define MIPS3_SR_PX 0x00800000 /* MIPS64 */
246 #define MIPS3_SR_SR 0x00100000
247 #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
248 #define MIPS3_SR_DIAG_CH 0x00040000
249 #define MIPS3_SR_DIAG_CE 0x00020000
250 #define MIPS3_SR_DIAG_PE 0x00010000
251 #define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
252 #define MIPS3_SR_KX 0x00000080
253 #define MIPS3_SR_SX 0x00000040
254 #define MIPS3_SR_UX 0x00000020
255 #define MIPS3_SR_KSU_MASK 0x00000018
256 #define MIPS3_SR_KSU_USER 0x00000010
257 #define MIPS3_SR_KSU_SUPER 0x00000008
258 #define MIPS3_SR_KSU_KERNEL 0x00000000
259 #define MIPS3_SR_ERL 0x00000004
260 #define MIPS3_SR_EXL 0x00000002
261
262 #ifdef MIPS3_5900
263 #undef MIPS_SR_INT_IE
264 #define MIPS_SR_INT_IE 0x00010001 /* XXX */
265 #endif
266
267 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
268 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
269 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
270 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
271 #define MIPS_SR_KX MIPS3_SR_KX
272 #define MIPS_SR_SX MIPS3_SR_SX
273 #define MIPS_SR_UX MIPS3_SR_UX
274
275 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
276 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
277 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
278 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
279 #define MIPS_SR_ERL MIPS3_SR_ERL
280 #define MIPS_SR_EXL MIPS3_SR_EXL
281
282
283 /*
284 * The interrupt masks.
285 * If a bit in the mask is 1 then the interrupt is enabled (or pending).
286 */
287 #define MIPS_INT_MASK 0xff00
288 #define MIPS_INT_MASK_5 0x8000
289 #define MIPS_INT_MASK_4 0x4000
290 #define MIPS_INT_MASK_3 0x2000
291 #define MIPS_INT_MASK_2 0x1000
292 #define MIPS_INT_MASK_1 0x0800
293 #define MIPS_INT_MASK_0 0x0400
294 #define MIPS_HARD_INT_MASK 0xfc00
295 #define MIPS_SOFT_INT_MASK_1 0x0200
296 #define MIPS_SOFT_INT_MASK_0 0x0100
297
298 /*
299 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
300 * choose to enable this interrupt.
301 */
302 #if defined(MIPS3_ENABLE_CLOCK_INTR)
303 #define MIPS3_INT_MASK MIPS_INT_MASK
304 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
305 #else
306 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
307 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
308 #endif
309
310 /*
311 * The bits in the context register.
312 */
313 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000
314 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
315
316 #define MIPS3_CNTXT_PTE_BASE 0xFF800000
317 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
318
319 /*
320 * The bits in the MIPS3 config register.
321 *
322 * bit 0..5: R/W, Bit 6..31: R/O
323 */
324
325 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
326 #define MIPS3_CONFIG_K0_MASK 0x00000007
327
328 /*
329 * R/W Update on Store Conditional
330 * 0: Store Conditional uses coherency algorithm specified by TLB
331 * 1: Store Conditional uses cacheable coherent update on write
332 */
333 #define MIPS3_CONFIG_CU 0x00000008
334
335 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
336 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
337 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
338 (((config) & (bit)) ? 32 : 16)
339
340 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
341 #define MIPS3_CONFIG_DC_SHIFT 6
342 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
343 #define MIPS3_CONFIG_IC_SHIFT 9
344 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
345
346 /* Cache size mode indication: available only on Vr41xx CPUs */
347 #define MIPS3_CONFIG_CS 0x00001000
348 #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
349 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
350 ((base) << (((config) & (mask)) >> (shift)))
351
352 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
353 #define MIPS3_CONFIG_SE 0x00001000
354
355 /* Block ordering: 0: sequential, 1: sub-block */
356 #define MIPS3_CONFIG_EB 0x00002000
357
358 /* ECC mode - 0: ECC mode, 1: parity mode */
359 #define MIPS3_CONFIG_EM 0x00004000
360
361 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
362 #define MIPS3_CONFIG_BE 0x00008000
363
364 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
365 #define MIPS3_CONFIG_SM 0x00010000
366
367 /* Secondary Cache - 0: present, 1: not present */
368 #define MIPS3_CONFIG_SC 0x00020000
369
370 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
371 #define MIPS3_CONFIG_EW_MASK 0x000c0000
372 #define MIPS3_CONFIG_EW_SHIFT 18
373
374 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
375 #define MIPS3_CONFIG_SW 0x00100000
376
377 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
378 #define MIPS3_CONFIG_SS 0x00200000
379
380 /* Secondary Cache line size */
381 #define MIPS3_CONFIG_SB_MASK 0x00c00000
382 #define MIPS3_CONFIG_SB_SHIFT 22
383 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
384 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
385
386 /* Write back data rate */
387 #define MIPS3_CONFIG_EP_MASK 0x0f000000
388 #define MIPS3_CONFIG_EP_SHIFT 24
389
390 /* System clock ratio - this value is CPU dependent */
391 #define MIPS3_CONFIG_EC_MASK 0x70000000
392 #define MIPS3_CONFIG_EC_SHIFT 28
393
394 /* Master-Checker Mode - 1: enabled */
395 #define MIPS3_CONFIG_CM 0x80000000
396
397 /*
398 * The bits in the MIPS4 config register.
399 */
400
401 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
402 #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
403 #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
404 #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
405 #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
406 #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
407 #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
408 #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
409 #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
410 #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
411 #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
412 #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
413 #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
414 #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
415 #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
416
417 #define MIPS4_CONFIG_DC_SHIFT 26
418 #define MIPS4_CONFIG_IC_SHIFT 29
419
420 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
421 ((base) << (((config) & (mask)) >> (shift)))
422
423 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
424 (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
425
426 /*
427 * Location of exception vectors.
428 *
429 * Common vectors: reset and UTLB miss.
430 */
431 #define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000)
432 #define MIPS_UTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0)
433
434 /*
435 * MIPS-1 general exception vector (everything else)
436 */
437 #define MIPS1_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
438
439 /*
440 * MIPS-III exception vectors
441 */
442 #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
443 #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
444 #define MIPS3_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0180)
445
446 /*
447 * TX79 (R5900) exception vectors
448 */
449 #define MIPS_R5900_COUNTER_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
450 #define MIPS_R5900_DEBUG_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
451
452 /*
453 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
454 */
455 #define MIPS3_INTR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0200)
456
457 /*
458 * Coprocessor 0 registers:
459 *
460 * v--- width for mips I,III,32,64
461 * (3=32bit, 6=64bit, i=impl dep)
462 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
463 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
464 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low.
465 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
466 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
467 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
468 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
469 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
470 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
471 * 9 MIPS_COP_0_COUNT .333 Count register.
472 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
473 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
474 * 12 MIPS_COP_0_STATUS 3333 Status register.
475 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
476 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
477 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
478 * 15/1 MIPS_COP_0_EBASE ..33 Exception Base
479 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
480 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
481 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
482 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
483 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
484 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
485 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
486 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
487 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
488 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
489 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
490 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
491 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
492 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
493 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
494 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
495 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
496 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
497 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
498 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
499 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
500 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
501 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
502 */
503 #ifdef _LOCORE
504 #define _(n) __CONCAT($,n)
505 #else
506 #define _(n) n
507 #endif
508 #define MIPS_COP_0_TLB_INDEX _(0)
509 #define MIPS_COP_0_TLB_RANDOM _(1)
510 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
511
512 #define MIPS_COP_0_TLB_CONTEXT _(4)
513 /* $5 and $6 new with MIPS-III */
514 #define MIPS_COP_0_BAD_VADDR _(8)
515 #define MIPS_COP_0_TLB_HI _(10)
516 #define MIPS_COP_0_STATUS _(12)
517 #define MIPS_COP_0_CAUSE _(13)
518 #define MIPS_COP_0_EXC_PC _(14)
519 #define MIPS_COP_0_PRID _(15)
520
521
522 /* MIPS-I */
523 #define MIPS_COP_0_TLB_LOW _(2)
524
525 /* MIPS-III */
526 #define MIPS_COP_0_TLB_LO0 _(2)
527 #define MIPS_COP_0_TLB_LO1 _(3)
528
529 #define MIPS_COP_0_TLB_PG_MASK _(5)
530 #define MIPS_COP_0_TLB_WIRED _(6)
531
532 #define MIPS_COP_0_COUNT _(9)
533 #define MIPS_COP_0_COMPARE _(11)
534
535 #define MIPS_COP_0_CONFIG _(16)
536 #define MIPS_COP_0_LLADDR _(17)
537 #define MIPS_COP_0_WATCH_LO _(18)
538 #define MIPS_COP_0_WATCH_HI _(19)
539 #define MIPS_COP_0_TLB_XCONTEXT _(20)
540 #define MIPS_COP_0_ECC _(26)
541 #define MIPS_COP_0_CACHE_ERR _(27)
542 #define MIPS_COP_0_TAG_LO _(28)
543 #define MIPS_COP_0_TAG_HI _(29)
544 #define MIPS_COP_0_ERROR_PC _(30)
545
546 /* MIPS32/64 */
547 #define MIPS_COP_0_DEBUG _(23)
548 #define MIPS_COP_0_DEPC _(24)
549 #define MIPS_COP_0_PERFCNT _(25)
550 #define MIPS_COP_0_DATA_LO _(28)
551 #define MIPS_COP_0_DATA_HI _(29)
552 #define MIPS_COP_0_DESAVE _(31)
553
554 /*
555 * Values for the code field in a break instruction.
556 */
557 #define MIPS_BREAK_INSTR 0x0000000d
558 #define MIPS_BREAK_VAL_MASK 0x03ff0000
559 #define MIPS_BREAK_VAL_SHIFT 16
560 #define MIPS_BREAK_KDB_VAL 512
561 #define MIPS_BREAK_SSTEP_VAL 513
562 #define MIPS_BREAK_BRKPT_VAL 514
563 #define MIPS_BREAK_SOVER_VAL 515
564 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
565 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
566 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
567 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
568 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
569 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
570 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
571 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
572
573 /*
574 * Mininum and maximum cache sizes.
575 */
576 #define MIPS_MIN_CACHE_SIZE (16 * 1024)
577 #define MIPS_MAX_CACHE_SIZE (256 * 1024)
578 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
579
580 /*
581 * The floating point version and status registers.
582 */
583 #define MIPS_FPU_ID $0
584 #define MIPS_FPU_CSR $31
585
586 /*
587 * The floating point coprocessor status register bits.
588 */
589 #define MIPS_FPU_ROUNDING_BITS 0x00000003
590 #define MIPS_FPU_ROUND_RN 0x00000000
591 #define MIPS_FPU_ROUND_RZ 0x00000001
592 #define MIPS_FPU_ROUND_RP 0x00000002
593 #define MIPS_FPU_ROUND_RM 0x00000003
594 #define MIPS_FPU_STICKY_BITS 0x0000007c
595 #define MIPS_FPU_STICKY_INEXACT 0x00000004
596 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
597 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
598 #define MIPS_FPU_STICKY_DIV0 0x00000020
599 #define MIPS_FPU_STICKY_INVALID 0x00000040
600 #define MIPS_FPU_ENABLE_BITS 0x00000f80
601 #define MIPS_FPU_ENABLE_INEXACT 0x00000080
602 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
603 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
604 #define MIPS_FPU_ENABLE_DIV0 0x00000400
605 #define MIPS_FPU_ENABLE_INVALID 0x00000800
606 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
607 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
608 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
609 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
610 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
611 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
612 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
613 #define MIPS_FPU_COND_BIT 0x00800000
614 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
615 #define MIPS1_FPC_MBZ_BITS 0xff7c0000
616 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000
617
618
619 /*
620 * Constants to determine if have a floating point instruction.
621 */
622 #define MIPS_OPCODE_SHIFT 26
623 #define MIPS_OPCODE_C1 0x11
624
625
626 /*
627 * The low part of the TLB entry.
628 */
629 #define MIPS1_TLB_PFN 0xfffff000
630 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
631 #define MIPS1_TLB_DIRTY_BIT 0x00000400
632 #define MIPS1_TLB_VALID_BIT 0x00000200
633 #define MIPS1_TLB_GLOBAL_BIT 0x00000100
634
635 #define MIPS3_TLB_PFN 0x3fffffc0
636 #define MIPS3_TLB_ATTR_MASK 0x00000038
637 #define MIPS3_TLB_ATTR_SHIFT 3
638 #define MIPS3_TLB_DIRTY_BIT 0x00000004
639 #define MIPS3_TLB_VALID_BIT 0x00000002
640 #define MIPS3_TLB_GLOBAL_BIT 0x00000001
641
642 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12
643 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6
644 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
645 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
646 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
647 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
648
649 /*
650 * MIPS3_TLB_ATTR values - coherency algorithm:
651 * 0: cacheable, noncoherent, write-through, no write allocate
652 * 1: cacheable, noncoherent, write-through, write allocate
653 * 2: uncached
654 * 3: cacheable, noncoherent, write-back (noncoherent)
655 * 4: cacheable, coherent, write-back, exclusive (exclusive)
656 * 5: cacheable, coherent, write-back, exclusive on write (sharable)
657 * 6: cacheable, coherent, write-back, update on write (update)
658 * 7: uncached, accelerated (gather STORE operations)
659 */
660 #define MIPS3_TLB_ATTR_WT 0 /* IDT */
661 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
662 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
663 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
664 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
665 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
666 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
667 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
668
669
670 /*
671 * The high part of the TLB entry.
672 */
673 #define MIPS1_TLB_VPN 0xfffff000
674 #define MIPS1_TLB_PID 0x00000fc0
675 #define MIPS1_TLB_PID_SHIFT 6
676
677 #define MIPS3_TLB_VPN2 0xffffe000
678 #define MIPS3_TLB_ASID 0x000000ff
679
680 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
681 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
682 #define MIPS3_TLB_PID MIPS3_TLB_ASID
683 #define MIPS_TLB_VIRT_PAGE_SHIFT 12
684
685 /*
686 * r3000: shift count to put the index in the right spot.
687 */
688 #define MIPS1_TLB_INDEX_SHIFT 8
689
690 /*
691 * The first TLB that write random hits.
692 */
693 #define MIPS1_TLB_FIRST_RAND_ENTRY 8
694 #define MIPS3_TLB_WIRED_UPAGES 1
695
696 /*
697 * The number of process id entries.
698 */
699 #define MIPS1_TLB_NUM_PIDS 64
700 #define MIPS3_TLB_NUM_ASIDS 256
701
702 /*
703 * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
704 */
705
706 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
707
708 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
709 && defined(MIPS1) /* XXX simonb must be neater! */
710 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
711 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
712 #endif
713
714 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
715 && !defined(MIPS1) /* XXX simonb must be neater! */
716 #define MIPS_TLB_PID_SHIFT 0
717 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
718 #endif
719
720
721 #if !defined(MIPS_TLB_PID_SHIFT)
722 #define MIPS_TLB_PID_SHIFT \
723 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
724
725 #define MIPS_TLB_NUM_PIDS \
726 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
727 #endif
728
729 /*
730 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
731 */
732 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
733 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
734 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
735 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
736 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
737 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
738 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
739 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
740 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
741 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
742 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
743 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
744 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
745 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
746 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
747 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
748 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
749 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
750 #define MIPS_R4650 0x22 /* QED R4650 ISA III */
751 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
752 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
753 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
754 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
755 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
756 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
757 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
758 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
759 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
760 #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/
761 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
762 #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
763 #define MIPS_LOONGSON2 0x63 /* ICT Loongson-2 ISA III */
764
765 /*
766 * CPU revision IDs for some prehistoric processors.
767 */
768
769 /* For MIPS_R3000 */
770 #define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */
771 #define MIPS_REV_R3000 0x20
772 #define MIPS_REV_R3000A 0x30
773
774 /* For MIPS_TX3900 */
775 #define MIPS_REV_TX3912 0x10
776 #define MIPS_REV_TX3922 0x30
777 #define MIPS_REV_TX3927 0x40
778
779 /* For MIPS_R4000 */
780 #define MIPS_REV_R4000_A 0x00
781 #define MIPS_REV_R4000_B 0x22
782 #define MIPS_REV_R4000_C 0x30
783 #define MIPS_REV_R4400_A 0x40
784 #define MIPS_REV_R4400_B 0x50
785 #define MIPS_REV_R4400_C 0x60
786
787 /* For MIPS_TX4900 */
788 #define MIPS_REV_TX4927 0x22
789
790 /* For MIPS_LOONGSON2 */
791 #define MIPS_REV_LOONGSON2E 0x02
792 #define MIPS_REV_LOONGSON2F 0x03
793
794 /*
795 * CPU processor revision IDs for company ID == 1 (MIPS)
796 */
797 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
798 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
799 #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
800 #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */
801 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
802 #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */
803 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
804 #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */
805 #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */
806 #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */
807 #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
808 #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
809 #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
810 #define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */
811 #define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */
812 #define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */
813 #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */
814
815 /*
816 * Alchemy (company ID 3) use the processor ID field to donote the CPU core
817 * revision and the company options field do donate the SOC chip type.
818 */
819 /* CPU processor revision IDs */
820 #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
821 #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
822 /* CPU company options IDs */
823 #define MIPS_AU1000 0x00
824 #define MIPS_AU1500 0x01
825 #define MIPS_AU1100 0x02
826 #define MIPS_AU1550 0x03
827
828 /*
829 * CPU processor revision IDs for company ID == 4 (SiByte)
830 */
831 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
832
833 /*
834 * CPU processor revision IDs for company ID == 5 (SandCraft)
835 */
836 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
837
838 /*
839 * CPU processor revision IDs for company ID == 12 (RMI)
840 */
841 #define MIPS_XLR732 0x00 /* RMI XLR732-C ISA 64 */
842 #define MIPS_XLR716 0x02 /* RMI XLR716-C ISA 64 */
843 #define MIPS_XLR532 0x08 /* RMI XLR532-C ISA 64 */
844 #define MIPS_XLR516 0x0a /* RMI XLR516-C ISA 64 */
845 #define MIPS_XLR508 0x0b /* RMI XLR508-C ISA 64 */
846 #define MIPS_XLR308 0x0f /* RMI XLR308-C ISA 64 */
847 #define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */
848 #define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */
849 #define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */
850 #define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */
851 #define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */
852 #define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */
853 #define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */
854 #define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */
855 #define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */
856 #define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */
857 #define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */
858
859 /*
860 * FPU processor revision ID
861 */
862 #define MIPS_SOFT 0x00 /* Software emulation ISA I */
863 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
864 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
865 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
866 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
867 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
868 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
869 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
870
871 #ifdef ENABLE_MIPS_TX3900
872 #include <mips/r3900regs.h>
873 #endif
874 #ifdef MIPS3_5900
875 #include <mips/r5900regs.h>
876 #endif
877 #ifdef MIPS64_SB1
878 #include <mips/sb1regs.h>
879 #endif
880 #if defined(MIPS64_XLP) || defined(MIPS64_XLR) || defined(MIPS64_XLS)
881 #include <mips/rmi/rmixlreg.h>
882 #endif
883
884 #endif /* _MIPS_CPUREGS_H_ */
NetBSD on the FriendlyARM MINI2440