sys/arch/mvme68k/dev/wdsc.c

   1 /*      $NetBSD: wdsc.c,v 1.30 2008/01/12 09:54:27 tsutsui Exp $        */
   2
   3 /*
   4  * Copyright (c) 1982, 1990 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of the University nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  *  @(#)wdsc.c
  32  */
  33
  34 /*-
  35  * Copyright (c) 1996-2004 The NetBSD Foundation, Inc.
  36  * All rights reserved.
  37  *
  38  * This code is derived from software contributed to The NetBSD Foundation
  39  * by Steve C. Woodford.
  40  *
  41  * Redistribution and use in source and binary forms, with or without
  42  * modification, are permitted provided that the following conditions
  43  * are met:
  44  * 1. Redistributions of source code must retain the above copyright
  45  *    notice, this list of conditions and the following disclaimer.
  46  * 2. Redistributions in binary form must reproduce the above copyright
  47  *    notice, this list of conditions and the following disclaimer in the
  48  *    documentation and/or other materials provided with the distribution.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  51  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  52  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  53  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  54  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  55  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  56  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  57  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  58  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  59  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  60  * POSSIBILITY OF SUCH DAMAGE.
  61  */
  62
  63 #include <sys/cdefs.h>
  64 __KERNEL_RCSID(0, "$NetBSD: wdsc.c,v 1.30 2008/01/12 09:54:27 tsutsui Exp $");
  65
  66 #include <sys/param.h>
  67 #include <sys/systm.h>
  68 #include <sys/kernel.h>
  69 #include <sys/device.h>
  70
  71 #include <dev/scsipi/scsi_all.h>
  72 #include <dev/scsipi/scsipi_all.h>
  73 #include <dev/scsipi/scsiconf.h>
  74
  75 #include <machine/cpu.h>
  76 #include <machine/bus.h>
  77 #include <machine/autoconf.h>
  78
  79 #include <mvme68k/dev/dmavar.h>
  80 #include <mvme68k/dev/pccreg.h>
  81 #include <mvme68k/dev/pccvar.h>
  82 #include <mvme68k/dev/sbicreg.h>
  83 #include <mvme68k/dev/sbicvar.h>
  84 #include <mvme68k/dev/wdscreg.h>
  85
  86 #include "ioconf.h"
  87
  88 void    wdsc_pcc_attach(struct device *, struct device *, void *);
  89 int     wdsc_pcc_match(struct device *, struct cfdata *, void *);
  90
  91 CFATTACH_DECL(wdsc_pcc, sizeof(struct sbic_softc),
  92     wdsc_pcc_match, wdsc_pcc_attach, NULL, NULL);
  93
  94 void    wdsc_enintr(struct sbic_softc *);
  95 int     wdsc_dmago(struct sbic_softc *, char *, int, int);
  96 int     wdsc_dmanext(struct sbic_softc *);
  97 void    wdsc_dmastop(struct sbic_softc *);
  98 int     wdsc_dmaintr(void *);
  99 int     wdsc_scsiintr(void *);
 100
 101 /*
 102  * Match for SCSI devices on the onboard WD33C93 chip
 103  */
 104 int
 105 wdsc_pcc_match(struct device *pdp, struct cfdata *cf, void *auxp)
 106 {
 107         struct pcc_attach_args *pa = auxp;
 108
 109         if (strcmp(pa->pa_name, wdsc_cd.cd_name))
 110                 return 0;
 111
 112         pa->pa_ipl = cf->pcccf_ipl;
 113         return 1;
 114 }
 115
 116 /*
 117  * Attach the wdsc driver
 118  */
 119 void
 120 wdsc_pcc_attach(struct device *pdp, struct device *dp, void *auxp)
 121 {
 122         struct sbic_softc *sc;
 123         struct pcc_attach_args *pa;
 124         bus_space_handle_t bush;
 125         static struct evcnt evcnt;      /* XXXSCW: Temporary hack */
 126
 127         sc = (struct sbic_softc *)dp;
 128         pa = auxp;
 129
 130         bus_space_map(pa->pa_bust, pa->pa_offset, 0x20, 0, &bush);
 131
 132         /*
 133          * XXXSCW: We *need* an MI, bus_spaced WD33C93 driver...
 134          */
 135         sc->sc_sbicp = (sbic_regmap_p) bush;
 136
 137         sc->sc_driver  = (void *) &evcnt;
 138         sc->sc_enintr  = wdsc_enintr;
 139         sc->sc_dmago   = wdsc_dmago;
 140         sc->sc_dmanext = wdsc_dmanext;
 141         sc->sc_dmastop = wdsc_dmastop;
 142         sc->sc_dmacmd  = 0;
 143
 144         sc->sc_adapter.adapt_dev = &sc->sc_dev;
 145         sc->sc_adapter.adapt_nchannels = 1;
 146         sc->sc_adapter.adapt_openings = 7;
 147         sc->sc_adapter.adapt_max_periph = 1;
 148         sc->sc_adapter.adapt_ioctl = NULL;
 149         sc->sc_adapter.adapt_minphys = sbic_minphys;
 150         sc->sc_adapter.adapt_request = sbic_scsi_request;
 151
 152         sc->sc_channel.chan_adapter = &sc->sc_adapter;
 153         sc->sc_channel.chan_bustype = &scsi_bustype;
 154         sc->sc_channel.chan_channel = 0;
 155         sc->sc_channel.chan_ntargets = 8;
 156         sc->sc_channel.chan_nluns = 8;
 157         sc->sc_channel.chan_id = 7;
 158
 159         printf(": WD33C93 SCSI, target %d\n", sc->sc_channel.chan_id);
 160
 161         /*
 162          * Everything is a valid DMA address.
 163          */
 164         sc->sc_dmamask = 0;
 165
 166         /*
 167          * The onboard WD33C93 of the '147 is usually clocked at 10MHz...
 168          * (We use 10 times this for accuracy in later calculations)
 169          */
 170         sc->sc_clkfreq = 100;
 171
 172         /*
 173          * Initialise the hardware
 174          */
 175         sbicinit(sc);
 176
 177         /*
 178          * Fix up the interrupts
 179          */
 180         sc->sc_ipl = pa->pa_ipl & PCC_IMASK;
 181
 182         pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, PCC_ICLEAR);
 183         pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, PCC_ICLEAR);
 184         pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0);
 185
 186         evcnt_attach_dynamic(&evcnt, EVCNT_TYPE_INTR, pccintr_evcnt(sc->sc_ipl),
 187             "disk", sc->sc_dev.dv_xname);
 188         pccintr_establish(PCCV_DMA, wdsc_dmaintr,  sc->sc_ipl, sc, &evcnt);
 189         pccintr_establish(PCCV_SCSI, wdsc_scsiintr, sc->sc_ipl, sc, &evcnt);
 190         pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL,
 191             sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
 192
 193         (void)config_found(dp, &sc->sc_channel, scsiprint);
 194 }
 195
 196 /*
 197  * Enable DMA interrupts
 198  */
 199 void
 200 wdsc_enintr(struct sbic_softc *dev)
 201 {
 202
 203         dev->sc_flags |= SBICF_INTR;
 204
 205         pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL,
 206             dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
 207 }
 208
 209 /*
 210  * Prime the hardware for a DMA transfer
 211  */
 212 int
 213 wdsc_dmago(struct sbic_softc *dev, char *addr, int count, int flags)
 214 {
 215
 216         /*
 217          * Set up the command word based on flags
 218          */
 219         if ((flags & DMAGO_READ) == 0)
 220                 dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE;
 221         else
 222                 dev->sc_dmacmd = DMAC_CSR_ENABLE;
 223
 224         dev->sc_flags |= SBICF_INTR;
 225         dev->sc_tcnt   = dev->sc_cur->dc_count << 1;
 226
 227         /*
 228          * Prime the hardware.
 229          * Note, it's probably not necessary to do this here, since dmanext
 230          * is called just prior to the actual transfer.
 231          */
 232         pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0);
 233         pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL,
 234             dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
 235         pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR,
 236             (uint32_t) dev->sc_cur->dc_addr);
 237         pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT,
 238             (uint32_t) dev->sc_tcnt | (1 << 24));
 239         pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd);
 240
 241         return dev->sc_tcnt;
 242 }
 243
 244 /*
 245  * Prime the hardware for the next DMA transfer
 246  */
 247 int
 248 wdsc_dmanext(struct sbic_softc *dev)
 249 {
 250
 251         if (dev->sc_cur > dev->sc_last) {
 252                 /*
 253                  * Shouldn't happen !!
 254                  */
 255                 printf("wdsc_dmanext at end !!!\n");
 256                 wdsc_dmastop(dev);
 257                 return 0;
 258         }
 259
 260         dev->sc_tcnt = dev->sc_cur->dc_count << 1;
 261
 262         /*
 263          * Load the next DMA address
 264          */
 265         pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0);
 266         pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL,
 267             dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
 268         pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR,
 269             (uint32_t) dev->sc_cur->dc_addr);
 270         pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT,
 271             (uint32_t) dev->sc_tcnt | (1 << 24));
 272         pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd);
 273
 274         return dev->sc_tcnt;
 275 }
 276
 277 /*
 278  * Stop DMA, and disable interrupts
 279  */
 280 void
 281 wdsc_dmastop(struct sbic_softc *dev)
 282 {
 283         int s;
 284
 285         s = splbio();
 286
 287         pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0);
 288         pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, dev->sc_ipl | PCC_ICLEAR);
 289
 290         splx(s);
 291 }
 292
 293 /*
 294  * Come here following a DMA interrupt
 295  */
 296 int
 297 wdsc_dmaintr(void *arg)
 298 {
 299         struct sbic_softc *dev = arg;
 300         int found = 0;
 301
 302         /*
 303          * Really a DMA interrupt?
 304          */
 305         if ((pcc_reg_read(sys_pcc, PCCREG_DMA_INTR_CTRL) & 0x80) == 0)
 306                 return 0;
 307
 308         /*
 309          * Was it a completion interrupt?
 310          * XXXSCW Note: Support for other DMA interrupts is required,
 311          * eg. buserr
 312          */
 313         if (pcc_reg_read(sys_pcc, PCCREG_DMA_CONTROL) & DMAC_CSR_DONE) {
 314                 ++found;
 315
 316                 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL,
 317                     dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
 318         }
 319
 320         return found;
 321 }
 322
 323 /*
 324  * Come here for SCSI interrupts
 325  */
 326 int
 327 wdsc_scsiintr(void *arg)
 328 {
 329         struct sbic_softc *dev = arg;
 330         int found;
 331
 332         /*
 333          * Really a SCSI interrupt?
 334          */
 335         if ((pcc_reg_read(sys_pcc, PCCREG_SCSI_INTR_CTRL) & 0x80) == 0)
 336                 return 0;
 337
 338         /*
 339          * Go handle it
 340          */
 341         found = sbicintr(dev);
 342
 343         /*
 344          * Acknowledge and clear the interrupt
 345          */
 346         pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL,
 347             dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR);
 348
 349         return found;
 350 }