sys/arch/newsmips/apbus/zs_ap.c

   1 /*      $NetBSD: zs_ap.c,v 1.24 2008/03/29 19:15:35 tsutsui Exp $       */
   2
   3 /*-
   4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Gordon W. Ross.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Zilog Z8530 Dual UART driver (machine-dependent part)
  34  *
  35  * Runs two serial lines per chip using slave drivers.
  36  * Plain tty/async lines use the zs_async slave.
  37  * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
  38  */
  39
  40 #include <sys/cdefs.h>
  41 __KERNEL_RCSID(0, "$NetBSD: zs_ap.c,v 1.24 2008/03/29 19:15:35 tsutsui Exp $");
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/device.h>
  46 #include <sys/tty.h>
  47 #include <sys/conf.h>
  48 #include <sys/cpu.h>
  49 #include <sys/intr.h>
  50
  51 #include <machine/adrsmap.h>
  52 #include <machine/z8530var.h>
  53
  54 #include <dev/cons.h>
  55 #include <dev/ic/z8530reg.h>
  56
  57 #include <newsmips/apbus/apbusvar.h>
  58
  59 #include "zsc.h"        /* NZSC */
  60 #define NZS NZSC
  61
  62 /* Make life easier for the initialized arrays here. */
  63 #if NZS < 2
  64 #undef  NZS
  65 #define NZS 2
  66 #endif
  67
  68 #define PORTB_XPORT     0x00000000
  69 #define PORTB_RPORT     0x00010000
  70 #define PORTA_XPORT     0x00020000
  71 #define PORTA_RPORT     0x00030000
  72 #define   DMA_MODE_REG          3
  73 #define     DMA_ENABLE          0x01    /* DMA enable */
  74 #define     DMA_DIR_DM          0x00    /* device to memory */
  75 #define     DMA_DIR_MD          0x02    /* memory to device */
  76 #define     DMA_EXTRDY          0x08    /* DMA external ready */
  77 #define PORTB_OFFSET    0x00040000
  78 #define PORTA_OFFSET    0x00050000
  79 #define   PORT_CTL              2
  80 #define     PORTCTL_RI          0x01
  81 #define     PORTCTL_DSR         0x02
  82 #define     PORTCTL_DTR         0x04
  83 #define   PORT_SEL              3
  84 #define     PORTSEL_LOCALTALK   0x01
  85 #define     PORTSEL_RS232C      0x02
  86 #define ESCC_REG        0x00060000
  87 #define   ESCCREG_INTSTAT       0
  88 #define     INTSTAT_SCC         0x01
  89 #define   ESCCREG_INTMASK       1
  90 #define     INTMASK_SCC         0x01
  91
  92 extern int zs_def_cflag;
  93 extern void (*zs_delay)(void);
  94
  95 /*
  96  * The news5000 provides a 9.8304 MHz clock to the ZS chips.
  97  */
  98 #define PCLK    (9600 * 1024)   /* PCLK pin input clock rate */
  99
 100 #define ZS_DELAY()      DELAY(2)
 101
 102 /* The layout of this is hardware-dependent (padding, order). */
 103 struct zschan {
 104         volatile uint8_t pad1[3];
 105         volatile uint8_t zc_csr;        /* ctrl,status, and indirect access */
 106         volatile uint8_t pad2[3];
 107         volatile uint8_t zc_data;       /* data */
 108 };
 109
 110 static void *zsaddr[NZS];
 111
 112 /* Flags from cninit() */
 113 static int zs_hwflags[NZS][2];
 114
 115 /* Default speed for all channels */
 116 static int zs_defspeed = 9600;
 117
 118 static uint8_t zs_init_reg[16] = {
 119         0,      /* 0: CMD (reset, etc.) */
 120         0,      /* 1: No interrupts yet. */
 121         0,      /* IVECT */
 122         ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
 123         ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
 124         ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
 125         0,      /* 6: TXSYNC/SYNCLO */
 126         0,      /* 7: RXSYNC/SYNCHI */
 127         0,      /* 8: alias for data port */
 128         ZSWR9_MASTER_IE,
 129         0,      /*10: Misc. TX/RX control bits */
 130         ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
 131         ((PCLK/32)/9600)-2,     /*12: BAUDLO (default=9600) */
 132         0,                      /*13: BAUDHI (default=9600) */
 133         ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
 134         ZSWR15_BREAK_IE,
 135 };
 136
 137 static struct zschan * zs_get_chan_addr(int, int);
 138 static void zs_ap_delay(void);
 139 static int zshard_ap(void *);
 140 static int zs_getc(void *);
 141 static void zs_putc(void *, int);
 142
 143 struct zschan *
 144 zs_get_chan_addr(int zs_unit, int channel)
 145 {
 146         void *addr;
 147         struct zschan *zc;
 148
 149         if (zs_unit >= NZS)
 150                 return NULL;
 151         addr = zsaddr[zs_unit];
 152         if (addr == NULL)
 153                 return NULL;
 154         if (channel == 0) {
 155                 zc = (void *)((uint8_t *)addr + PORTA_OFFSET);
 156         } else {
 157                 zc = (void *)((uint8_t *)addr + PORTB_OFFSET);
 158         }
 159         return zc;
 160 }
 161
 162 void
 163 zs_ap_delay(void)
 164 {
 165
 166         ZS_DELAY();
 167 }
 168
 169 /****************************************************************
 170  * Autoconfig
 171  ****************************************************************/
 172
 173 /* Definition of the driver for autoconfig. */
 174 int zs_ap_match(device_t, cfdata_t, void *);
 175 void zs_ap_attach(device_t, device_t, void *);
 176
 177 CFATTACH_DECL_NEW(zsc_ap, sizeof(struct zsc_softc),
 178     zs_ap_match, zs_ap_attach, NULL, NULL);
 179
 180 /*
 181  * Is the zs chip present?
 182  */
 183 int
 184 zs_ap_match(device_t parent, cfdata_t cf, void *aux)
 185 {
 186         struct apbus_attach_args *apa = aux;
 187
 188         if (strcmp("esccf", apa->apa_name) != 0)
 189                 return 0;
 190
 191         return 1;
 192 }
 193
 194 /*
 195  * Attach a found zs.
 196  *
 197  * Match slave number to zs unit number, so that misconfiguration will
 198  * not set up the keyboard as ttya, etc.
 199  */
 200 void
 201 zs_ap_attach(device_t parent, device_t self, void *aux)
 202 {
 203         struct zsc_softc *zsc = device_private(self);
 204         struct apbus_attach_args *apa = aux;
 205         struct zsc_attach_args zsc_args;
 206         volatile struct zschan *zc;
 207         struct zs_chanstate *cs;
 208         int s, zs_unit, channel;
 209         volatile u_int *txBfifo = (void *)(apa->apa_hwbase + PORTB_XPORT);
 210         volatile u_int *rxBfifo = (void *)(apa->apa_hwbase + PORTB_RPORT);
 211         volatile u_int *txAfifo = (void *)(apa->apa_hwbase + PORTA_XPORT);
 212         volatile u_int *rxAfifo = (void *)(apa->apa_hwbase + PORTA_RPORT);
 213         volatile u_int *portBctl = (void *)(apa->apa_hwbase + PORTB_OFFSET);
 214         volatile u_int *portActl = (void *)(apa->apa_hwbase + PORTA_OFFSET);
 215         volatile u_int *esccregs = (void *)(apa->apa_hwbase + ESCC_REG);
 216         static int didintr;
 217
 218         zsc->zsc_dev = self;
 219         zs_unit = device_unit(self);
 220         zsaddr[zs_unit] = (void *)apa->apa_hwbase;
 221
 222         aprint_normal(" slot%d addr 0x%lx\n", apa->apa_slotno, apa->apa_hwbase);
 223
 224         txAfifo[DMA_MODE_REG] = rxAfifo[DMA_MODE_REG] = DMA_EXTRDY;
 225         txBfifo[DMA_MODE_REG] = rxBfifo[DMA_MODE_REG] = DMA_EXTRDY;
 226
 227         /* assert DTR */                        /* XXX */
 228         portBctl[PORT_CTL] = portActl[PORT_CTL] = PORTCTL_DTR;
 229
 230         /* select RS-232C (ch1 only) */
 231         portActl[PORT_SEL] = PORTSEL_RS232C;
 232
 233         /* enable SCC interrupts */
 234         esccregs[ESCCREG_INTMASK] = INTMASK_SCC;
 235
 236         zs_delay = zs_ap_delay;
 237
 238         /*
 239          * Initialize software state for each channel.
 240          */
 241         for (channel = 0; channel < 2; channel++) {
 242                 zsc_args.channel = channel;
 243                 zsc_args.hwflags = zs_hwflags[zs_unit][channel];
 244                 cs = &zsc->zsc_cs_store[channel];
 245                 zsc->zsc_cs[channel] = cs;
 246
 247                 zs_lock_init(cs);
 248                 cs->cs_channel = channel;
 249                 cs->cs_private = NULL;
 250                 cs->cs_ops = &zsops_null;
 251                 cs->cs_brg_clk = PCLK / 16;
 252
 253                 zc = zs_get_chan_addr(zs_unit, channel);
 254                 cs->cs_reg_csr  = &zc->zc_csr;
 255                 cs->cs_reg_data = &zc->zc_data;
 256
 257                 memcpy(cs->cs_creg, zs_init_reg, 16);
 258                 memcpy(cs->cs_preg, zs_init_reg, 16);
 259
 260                 /* XXX: Get these from the EEPROM instead? */
 261                 /* XXX: See the mvme167 code.  Better. */
 262                 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
 263                         cs->cs_defspeed = zs_get_speed(cs);
 264                 else
 265                         cs->cs_defspeed = zs_defspeed;
 266                 cs->cs_defcflag = zs_def_cflag;
 267
 268                 /* Make these correspond to cs_defcflag (-crtscts) */
 269                 cs->cs_rr0_dcd = ZSRR0_DCD;
 270                 cs->cs_rr0_cts = 0;
 271                 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
 272                 cs->cs_wr5_rts = 0;
 273
 274                 /*
 275                  * Clear the master interrupt enable.
 276                  * The INTENA is common to both channels,
 277                  * so just do it on the A channel.
 278                  */
 279                 if (channel == 0) {
 280                         zs_write_reg(cs, 9, 0);
 281                 }
 282
 283                 /*
 284                  * Look for a child driver for this channel.
 285                  * The child attach will setup the hardware.
 286                  */
 287                 if (!config_found(self, (void *)&zsc_args, zs_print)) {
 288                         /* No sub-driver.  Just reset it. */
 289                         uint8_t reset = (channel == 0) ?
 290                             ZSWR9_A_RESET : ZSWR9_B_RESET;
 291                         s = splhigh();
 292                         zs_write_reg(cs, 9, reset);
 293                         splx(s);
 294                 }
 295         }
 296
 297         /*
 298          * Now safe to install interrupt handlers.  Note the arguments
 299          * to the interrupt handlers aren't used.  Note, we only do this
 300          * once since both SCCs interrupt at the same level and vector.
 301          */
 302         if (!didintr) {
 303                 didintr = 1;
 304
 305                 zsc->zsc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc);
 306                 apbus_intr_establish(1, /* interrupt level ( 0 or 1 ) */
 307                                      NEWS5000_INT1_SCC,
 308                                      0, /* priority */
 309                                      zshard_ap, zsc,
 310                                      apa->apa_name, apa->apa_ctlnum);
 311         }
 312         /* XXX; evcnt_attach() ? */
 313
 314 #if 0
 315 {
 316         u_int x;
 317
 318         /* determine SCC/ESCC type */
 319         x = zs_read_reg(cs, 15);
 320         zs_write_reg(cs, 15, x | ZSWR15_ENABLE_ENHANCED);
 321
 322         if (zs_read_reg(cs, 15) & ZSWR15_ENABLE_ENHANCED) { /* ESCC Z85230 */
 323                 zs_write_reg(cs, 7, ZSWR7P_EXTEND_READ | ZSWR7P_TX_FIFO);
 324         }
 325 }
 326 #endif
 327
 328         /*
 329          * Set the master interrupt enable and interrupt vector.
 330          * (common to both channels, do it on A)
 331          */
 332         cs = zsc->zsc_cs[0];
 333         s = splhigh();
 334         /* interrupt vector */
 335         zs_write_reg(cs, 2, zs_init_reg[2]);
 336         /* master interrupt control (enable) */
 337         zs_write_reg(cs, 9, zs_init_reg[9]);
 338         splx(s);
 339 }
 340
 341 static int
 342 zshard_ap(void *arg)
 343 {
 344
 345         zshard(arg);
 346         return 1;
 347 }
 348
 349 /*
 350  * Polled input char.
 351  */
 352 int
 353 zs_getc(void *arg)
 354 {
 355         volatile struct zschan *zc = arg;
 356         int s, c;
 357         uint8_t rr0;
 358
 359         s = splhigh();
 360         /* Wait for a character to arrive. */
 361         do {
 362                 rr0 = zc->zc_csr;
 363                 ZS_DELAY();
 364         } while ((rr0 & ZSRR0_RX_READY) == 0);
 365
 366         c = zc->zc_data;
 367         ZS_DELAY();
 368         splx(s);
 369
 370         /*
 371          * This is used by the kd driver to read scan codes,
 372          * so don't translate '\r' ==> '\n' here...
 373          */
 374         return c;
 375 }
 376
 377 /*
 378  * Polled output char.
 379  */
 380 void
 381 zs_putc(void *arg, int c)
 382 {
 383         volatile struct zschan *zc = arg;
 384         int s;
 385         uint8_t rr0;
 386
 387         s = splhigh();
 388         /* Wait for transmitter to become ready. */
 389         do {
 390                 rr0 = zc->zc_csr;
 391                 ZS_DELAY();
 392         } while ((rr0 & ZSRR0_TX_READY) == 0);
 393
 394         zc->zc_data = c;
 395         ZS_DELAY();
 396         splx(s);
 397 }
 398
 399 /*****************************************************************/
 400
 401 static void zscnprobe(struct consdev *);
 402 static void zscninit(struct consdev *);
 403 static int  zscngetc(dev_t);
 404 static void zscnputc(dev_t, int);
 405
 406 struct consdev consdev_zs_ap = {
 407         zscnprobe,
 408         zscninit,
 409         zscngetc,
 410         zscnputc,
 411         nullcnpollc,
 412         NULL,
 413         NULL,
 414         NULL,
 415         NODEV,
 416         CN_DEAD
 417 };
 418
 419 static void
 420 zscnprobe(struct consdev *cn)
 421 {
 422 }
 423
 424 static void
 425 zscninit(struct consdev *cn)
 426 {
 427         extern const struct cdevsw zstty_cdevsw;
 428
 429         cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
 430         cn->cn_pri = CN_REMOTE;
 431         zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE;
 432 }
 433
 434 static int
 435 zscngetc(dev_t dev)
 436 {
 437
 438         return zs_getc((void *)NEWS5000_SCCPORT0A);
 439 }
 440
 441 static void
 442 zscnputc(dev_t dev, int c)
 443 {
 444
 445         zs_putc((void *)NEWS5000_SCCPORT0A, c);
 446 }