sys/arch/newsmips/dev/screg_1185.h

   1 /*      $NetBSD: screg_1185.h,v 1.6 2005/12/11 12:18:24 christos Exp $  */
   2 /*
   3  * Copyright (c) 1992, 1993
   4  *      The Regents of the University of California.  All rights reserved.
   5  *
   6  * This code is derived from software contributed to Berkeley by
   7  * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  * from: $Hdr: screg_1185.h,v 4.300 91/06/09 06:22:14 root Rel41 $ SONY
  34  *
  35  *      @(#)screg_1185.h        8.1 (Berkeley) 6/11/93
  36  */
  37
  38 /*
  39  * Copyright (c) 1989- by SONY Corporation.
  40  */
  41
  42 /*
  43  *      screg_1185.h    ver 0.0
  44  *              for SCSI I/F Chip CXD1185Q
  45  */
  46
  47 /*
  48  *              SCSI I/F Chip CXD1185Q Register address assignment
  49  */
  50 #ifdef __mips__
  51 # define        SCSI_BASE       0xbfe00100
  52 #else
  53 # define        SCSI_BASE       0xe1900000
  54 #endif
  55
  56 #define sc_statr        *((volatile uint8_t *)(SCSI_BASE + 0x0))
  57 #define sc_comr         *((volatile uint8_t *)(SCSI_BASE + 0x0))
  58 #define sc_datr         *((volatile uint8_t *)(SCSI_BASE + 0x1))
  59 #define sc_intrq1       *((volatile uint8_t *)(SCSI_BASE + 0x2))
  60 #define sc_intrq2       *((volatile uint8_t *)(SCSI_BASE + 0x3))
  61 #define sc_envir        *((volatile uint8_t *)(SCSI_BASE + 0x3))
  62 #define sc_cmonr        *((volatile uint8_t *)(SCSI_BASE + 0x4))
  63 #define sc_timer        *((volatile uint8_t *)(SCSI_BASE + 0x4))
  64 #define sc_ffstr        *((volatile uint8_t *)(SCSI_BASE + 0x5))
  65 #define sc_idenr        *((volatile uint8_t *)(SCSI_BASE + 0x6))
  66 #define sc_tclow        *((volatile uint8_t *)(SCSI_BASE + 0x7))
  67 #define sc_tcmid        *((volatile uint8_t *)(SCSI_BASE + 0x8))
  68 #define sc_tchi         *((volatile uint8_t *)(SCSI_BASE + 0x9))
  69 #define sc_intok1       *((volatile uint8_t *)(SCSI_BASE + 0xa))
  70 #define sc_intok2       *((volatile uint8_t *)(SCSI_BASE + 0xb))
  71 #define sc_moder        *((volatile uint8_t *)(SCSI_BASE + 0xc))
  72 #define sc_syncr        *((volatile uint8_t *)(SCSI_BASE + 0xd))
  73 #define sc_busconr      *((volatile uint8_t *)(SCSI_BASE + 0xe))
  74 #define sc_ioptr        *((volatile uint8_t *)(SCSI_BASE + 0xf))
  75
  76 /*
  77  *              CXD1185Q Register bit assignment
  78  */
  79
  80 /*      sc_statr (status register) bit define
  81 */
  82 #define R0_MRST         0x80
  83 #define R0_MDBP         0x40
  84 #define R0_INIT         0x10
  85 #define R0_TARG         8
  86 #define R0_TRBZ         4
  87 #define R0_MIRQ         2
  88 #define R0_CIP          1
  89
  90 /*      sc_comr (command register) bit define
  91 */
  92 #define R0_DMA          0x20
  93 #define R0_TRBE         0x10
  94
  95 /*      sc_intrq1 (interrupt request register 1) bit define
  96 */
  97 #define R2_STO          0x10
  98 #define R2_RSL          8
  99 #define R2_SWA          4
 100 #define R2_SWOA         2
 101 #define R2_ARBF         1
 102
 103 /*      sc_intrq2 (interrupt request register 2) bit define
 104 */
 105 #define R3_FNC          0x80
 106 #define R3_DCNT         0x40
 107 #define R3_SRST         0x20
 108 #define R3_PHC          0x10
 109 #define R3_DATN         8
 110 #define R3_DPE          4
 111 #define R3_SPE          2
 112 #define R3_RMSG         1
 113
 114 /*      sc_envir (environment register) bit define
 115 */
 116 #define R3_DIFE         0x80
 117 #define R3_SDPM         0x40
 118 #define R3_DPEN         0x20
 119 #define R3_SIRM         0x10
 120 #define R3_FS_MASK      3
 121
 122 /*      sc_cmonr (scsi control monitor register) bit define
 123 */
 124 #define R4_MBSY         0x80
 125 #define R4_MSEL         0x40
 126 #define R4_MMSG         0x20
 127 #define R4_MCD          0x10
 128 #define R4_MIO          8
 129 #define R4_MREQ         4
 130 #define R4_MACK         2
 131 #define R4_MATN         1
 132
 133 /*      sc_ffstr (FIFO status register) bit define
 134 */
 135 #define R5_FIE          0x80
 136 #define R5_FIF          0x10
 137 #define R5_FIFOREM      0x1f
 138
 139 /*      sc_idenr (scsi identify register) bit define
 140 */
 141 #define R6_OID_MASK     0x07
 142 #define R6_SID_MASK     0xe0
 143 #define R6_TID_MASK     0xe0
 144
 145 /*      sc_intok1 (interrupt enable register 1) bit define
 146 */
 147 #define Ra_STO          0x10
 148 #define Ra_RSL          8
 149 #define Ra_SWA          4
 150 #define Ra_SWOA         2
 151 #define Ra_ARBF         1
 152
 153 /*      sc_intok2 (interrupt enable register 2) bit define
 154 */
 155 #define Rb_FNC          0x80
 156 #define Rb_DCNT         0x40
 157 #define Rb_SRST         0x20
 158 #define Rb_PHC          0x10
 159 #define Rb_DATN         8
 160 #define Rb_DPE          4
 161 #define Rb_SPE          2
 162 #define Rb_RMSG         1
 163
 164 /*      sc_moder (mode register) bit define
 165 */
 166 #define Rc_HDPE         0x80
 167 #define Rc_HSPE         0x40
 168 #define Rc_HATN         0x20
 169 #define Rc_TMSL         0x10
 170 #define Rc_SPHI         8
 171 #define Rc_BDMA         1
 172
 173 /*      sc_syncr (synchronous transfer control register) bit define
 174 */
 175 #define Rd_TPD_MASK     0xf0
 176 #define Rd_TOF_MASK     0x0f
 177 #define MIN_TP          62              /* minimum transfer period 4ns * 25 */
 178 #define MAX_OFFSET      15
 179
 180 /*      sc_busconr (scsi bus control register) bit define
 181 */
 182 #define Re_ABSY         0x80
 183 #define Re_ASEL         0x40
 184 #define Re_AMSG         0x20
 185 #define Re_ACD          0x10
 186 #define Re_AIO          8
 187 #define Re_AREQ         4
 188 #define Re_AACK         2
 189 #define Re_AATN         1
 190
 191 /*      sc_ioptr (I/O port) bit define
 192 */
 193 #define Rf_PCN_MASK     0xf0
 194 # define        Rf_PCN3         0x80
 195 # define        Rf_PCN2         0x40
 196 # define        Rf_PCN1         0x20
 197 # define        Rf_PCN0         0x10
 198 #define Rf_PRT_MASK     0x0f
 199 # define        Rf_PRT3         8
 200 # define        Rf_PRT2         4
 201 # define        Rf_PRT1         2
 202 # define        Rf_PRT0         1
 203
 204
 205 /*
 206  *              CXD1185Q commands
 207  */
 208 /*      category 0
 209 */
 210 #define SCMD_NOP        0x00
 211 #define SCMD_CHIP_RST   0x01
 212 #define SCMD_AST_RST    0x02
 213 #define SCMD_FLSH_FIFO  0x03
 214 #define SCMD_AST_CTRL   0x04
 215 #define SCMD_NGT_CTRL   0x05
 216 #define SCMD_AST_DATA   0x06
 217 #define SCMD_NGT_DATA   0x07
 218
 219 /*      category 1
 220 */
 221 #define SCMD_RESEL      0x40
 222 #define SCMD_SEL        0x41
 223 #define SCMD_SEL_ATN    0x42
 224 #define SCMD_ENB_SEL    0x43
 225 #define SCMD_DIS_SEL    0x44
 226
 227 /*      category 2
 228 */
 229 #define SCMD_SEND_MES   0x80
 230 #define SCMD_SEND_STAT  0x81
 231 #define SCMD_SEND_DATA  0x82
 232 #define SCMD_DISCONNECT 0x83
 233 #define SCMD_RCV_MOUT   0x84
 234 #define SCMD_RCV_CMD    0x85
 235 #define SCMD_RCV_DATA   0x86
 236
 237 /*      category 3
 238 */
 239 #define SCMD_TR_INFO    0xc0
 240 #define SCMD_TR_PAD     0xc1
 241 #define SCMD_NGT_ACK    0xc2
 242 #define SCMD_AST_ATN    0xc3
 243 #define SCMD_NGT_ATN    0xc4
 244
 245
 246 /*
 247  *              scsi parameter definition
 248  */
 249 /*      SCSI bus ID
 250 */
 251 #define SC_OWNID        0x7
 252 #define SC_TG_SHIFT     5
 253
 254 /*      scsi bus phase
 255 */
 256 #define SC_PMASK                (R4_MMSG|R4_MCD|R4_MIO)
 257 # define        DAT_OUT         0
 258 # define        DAT_IN                          R4_MIO
 259 # define        COM_OUT                  R4_MCD
 260 # define        STAT_IN                 (R4_MCD|R4_MIO)
 261 # define        MES_OUT         (R4_MMSG|R4_MCD)
 262 # define        MES_IN          (R4_MMSG|R4_MCD|R4_MIO)
 263
 264 /*      scsi command types define
 265 */
 266 #define CMD_TYPEMASK    0xe0
 267 # define        CMD_T0          0               /*  6 byte commands */
 268 # define        CMD_T1          0x20            /* 10 byte commands */
 269 # define        CMD_T5          0xa0            /* 12 byte commands */
 270 # define        CMD_T6          0xc0
 271 # define        CMD_T7          0xe0
 272
 273 #define MAXNSCSI        1