sys/arch/newsmips/dev/zs.c

   1 /*      $NetBSD: zs.c,v 1.24 2008/04/28 20:23:30 martin Exp $   */
   2
   3 /*-
   4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Gordon W. Ross.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Zilog Z8530 Dual UART driver (machine-dependent part)
  34  *
  35  * Runs two serial lines per chip using slave drivers.
  36  * Plain tty/async lines use the zs_async slave.
  37  * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
  38  */
  39
  40 #include <sys/cdefs.h>
  41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.24 2008/04/28 20:23:30 martin Exp $");
  42
  43 #include "opt_ddb.h"
  44
  45 #include <sys/param.h>
  46 #include <sys/device.h>
  47 #include <sys/tty.h>
  48 #include <sys/systm.h>
  49 #include <sys/cpu.h>
  50 #include <sys/intr.h>
  51
  52 #include <machine/adrsmap.h>
  53 #include <machine/z8530var.h>
  54
  55 #include <dev/ic/z8530reg.h>
  56
  57 #include "ioconf.h"
  58
  59 #define ZS_DELAY() (*zs_delay)()
  60
  61 /*
  62  * Some warts needed by z8530tty.c -
  63  * The default parity REALLY needs to be the same as the PROM uses,
  64  * or you can not see messages done with printf during boot-up...
  65  */
  66 int zs_def_cflag = (CREAD | CS8 | HUPCL);
  67
  68 int
  69 zs_print(void *aux, const char *name)
  70 {
  71         struct zsc_attach_args *args = aux;
  72
  73         if (name != NULL)
  74                 aprint_normal("%s: ", name);
  75
  76         if (args->channel != -1)
  77                 aprint_normal(" channel %d", args->channel);
  78
  79         return UNCONF;
  80 }
  81
  82 /*
  83  * Our ZS chips all share a common, autovectored interrupt,
  84  * so we have to look at all of them on each interrupt.
  85  */
  86 int
  87 zshard(void *arg)
  88 {
  89         struct zsc_softc *zsc;
  90         int unit, rval, softreq;
  91
  92         rval = 0;
  93         for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
  94                 zsc = device_lookup_private(&zsc_cd, unit);
  95                 if (zsc == NULL)
  96                         continue;
  97                 rval |= zsc_intr_hard(zsc);
  98                 softreq =  zsc->zsc_cs[0]->cs_softreq;
  99                 softreq |= zsc->zsc_cs[1]->cs_softreq;
 100                 if (softreq)
 101                         softint_schedule(zsc->zsc_si);
 102         }
 103
 104         return rval;
 105 }
 106
 107 /*
 108  * Similar scheme as for zshard (look at all of them)
 109  */
 110 void
 111 zssoft(void *arg)
 112 {
 113         struct zsc_softc *zsc;
 114         int s, unit;
 115
 116         /* Make sure we call the tty layer at spltty. */
 117         s = spltty();
 118         for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
 119                 zsc = device_lookup_private(&zsc_cd, unit);
 120                 if (zsc == NULL)
 121                         continue;
 122                 (void)zsc_intr_soft(zsc);
 123         }
 124         splx(s);
 125 }
 126
 127 /*
 128  * Compute the current baud rate given a ZS channel.
 129  */
 130 int
 131 zs_get_speed(struct zs_chanstate *cs)
 132 {
 133         int tconst;
 134
 135         tconst = zs_read_reg(cs, 12);
 136         tconst |= zs_read_reg(cs, 13) << 8;
 137         return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
 138 }
 139
 140 /*
 141  * MD functions for setting the baud rate and control modes.
 142  */
 143 int
 144 zs_set_speed(struct zs_chanstate *cs, int bps)
 145 {
 146         int tconst, real_bps;
 147
 148         if (bps == 0)
 149                 return 0;
 150
 151 #ifdef  DIAGNOSTIC
 152         if (cs->cs_brg_clk == 0)
 153                 panic("zs_set_speed");
 154 #endif
 155
 156         tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
 157         if (tconst < 0)
 158                 return EINVAL;
 159
 160         /* Convert back to make sure we can do it. */
 161         real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
 162
 163         /* XXX - Allow some tolerance here? */
 164         if (real_bps != bps)
 165                 return EINVAL;
 166
 167         cs->cs_preg[12] = tconst;
 168         cs->cs_preg[13] = tconst >> 8;
 169
 170         /* Caller will stuff the pending registers. */
 171         return 0;
 172 }
 173
 174 int
 175 zs_set_modes(struct zs_chanstate *cs, int cflag)
 176 {
 177         int s;
 178
 179         /*
 180          * Output hardware flow control on the chip is horrendous:
 181          * if carrier detect drops, the receiver is disabled, and if
 182          * CTS drops, the transmitter is stoped IN MID CHARACTER!
 183          * Therefore, NEVER set the HFC bit, and instead use the
 184          * status interrupt to detect CTS changes.
 185          */
 186         s = splserial();
 187         cs->cs_rr0_pps = 0;
 188         if ((cflag & (CLOCAL | MDMBUF)) != 0) {
 189                 cs->cs_rr0_dcd = 0;
 190                 if ((cflag & MDMBUF) == 0)
 191                         cs->cs_rr0_pps = ZSRR0_DCD;
 192         } else
 193                 cs->cs_rr0_dcd = ZSRR0_DCD;
 194         if ((cflag & CRTSCTS) != 0) {
 195                 cs->cs_wr5_dtr = ZSWR5_DTR;
 196                 cs->cs_wr5_rts = ZSWR5_RTS;
 197                 cs->cs_rr0_cts = ZSRR0_CTS;
 198         } else if ((cflag & MDMBUF) != 0) {
 199                 cs->cs_wr5_dtr = 0;
 200                 cs->cs_wr5_rts = ZSWR5_DTR;
 201                 cs->cs_rr0_cts = ZSRR0_DCD;
 202         } else {
 203                 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
 204                 cs->cs_wr5_rts = 0;
 205                 cs->cs_rr0_cts = 0;
 206         }
 207         splx(s);
 208
 209         /* Caller will stuff the pending registers. */
 210         return 0;
 211 }
 212
 213 /*
 214  * Read or write the chip with suitable delays.
 215  */
 216
 217 uint8_t
 218 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
 219 {
 220         uint8_t val;
 221
 222         *cs->cs_reg_csr = reg;
 223         ZS_DELAY();
 224         val = *cs->cs_reg_csr;
 225         ZS_DELAY();
 226         return val;
 227 }
 228
 229 void
 230 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
 231 {
 232
 233         *cs->cs_reg_csr = reg;
 234         ZS_DELAY();
 235         *cs->cs_reg_csr = val;
 236         ZS_DELAY();
 237 }
 238
 239 uint8_t
 240 zs_read_csr(struct zs_chanstate *cs)
 241 {
 242         uint8_t val;
 243
 244         val = *cs->cs_reg_csr;
 245         ZS_DELAY();
 246         return val;
 247 }
 248
 249 void
 250 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
 251 {
 252
 253         *cs->cs_reg_csr = val;
 254         ZS_DELAY();
 255 }
 256
 257 uint8_t
 258  zs_read_data(struct zs_chanstate *cs)
 259 {
 260         uint8_t val;
 261
 262         val = *cs->cs_reg_data;
 263         ZS_DELAY();
 264         return val;
 265 }
 266
 267 void
 268 zs_write_data(struct zs_chanstate *cs, uint8_t val)
 269 {
 270
 271         *cs->cs_reg_data = val;
 272         ZS_DELAY();
 273 }
 274
 275 void
 276 zs_abort(struct zs_chanstate *cs)
 277 {
 278
 279 #ifdef DDB
 280         Debugger();
 281 #endif
 282 }