sys/arch/powerpc/fpu/fpu_explode.c

   1 /*      $NetBSD: fpu_explode.c,v 1.1.24.3 2004/09/21 13:20:34 skrll Exp $ */
   2
   3 /*
   4  * Copyright (c) 1992, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This software was developed by the Computer Systems Engineering group
   8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
   9  * contributed to Berkeley.
  10  *
  11  * All advertising materials mentioning features or use of this software
  12  * must display the following acknowledgement:
  13  *      This product includes software developed by the University of
  14  *      California, Lawrence Berkeley Laboratory.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  * 3. Neither the name of the University nor the names of its contributors
  25  *    may be used to endorse or promote products derived from this software
  26  *    without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  *      @(#)fpu_explode.c       8.1 (Berkeley) 6/11/93
  41  */
  42
  43 /*
  44  * FPU subroutines: `explode' the machine's `packed binary' format numbers
  45  * into our internal format.
  46  */
  47
  48 #include <sys/cdefs.h>
  49 __KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.1.24.3 2004/09/21 13:20:34 skrll Exp $");
  50
  51 #include <sys/types.h>
  52 #include <sys/systm.h>
  53
  54 #include <machine/ieee.h>
  55 #include <powerpc/instr.h>
  56 #include <machine/reg.h>
  57 #include <machine/fpu.h>
  58
  59 #include <powerpc/fpu/fpu_arith.h>
  60 #include <powerpc/fpu/fpu_emu.h>
  61 #include <powerpc/fpu/fpu_extern.h>
  62
  63 /*
  64  * N.B.: in all of the following, we assume the FP format is
  65  *
  66  *      ---------------------------
  67  *      | s | exponent | fraction |
  68  *      ---------------------------
  69  *
  70  * (which represents -1**s * 1.fraction * 2**exponent), so that the
  71  * sign bit is way at the top (bit 31), the exponent is next, and
  72  * then the remaining bits mark the fraction.  A zero exponent means
  73  * zero or denormalized (0.fraction rather than 1.fraction), and the
  74  * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
  75  *
  76  * Since the sign bit is always the topmost bit---this holds even for
  77  * integers---we set that outside all the *tof functions.  Each function
  78  * returns the class code for the new number (but note that we use
  79  * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
  80  */
  81
  82 /*
  83  * int -> fpn.
  84  */
  85 int
  86 fpu_itof(struct fpn *fp, u_int i)
  87 {
  88
  89         if (i == 0)
  90                 return (FPC_ZERO);
  91         /*
  92          * The value FP_1 represents 2^FP_LG, so set the exponent
  93          * there and let normalization fix it up.  Convert negative
  94          * numbers to sign-and-magnitude.  Note that this relies on
  95          * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
  96          */
  97         fp->fp_exp = FP_LG;
  98         fp->fp_mant[0] = (int)i < 0 ? -i : i;
  99         fp->fp_mant[1] = 0;
 100         fp->fp_mant[2] = 0;
 101         fp->fp_mant[3] = 0;
 102         fpu_norm(fp);
 103         return (FPC_NUM);
 104 }
 105
 106 /*
 107  * 64-bit int -> fpn.
 108  */
 109 int
 110 fpu_xtof(struct fpn *fp, u_int64_t i)
 111 {
 112
 113         if (i == 0)
 114                 return (FPC_ZERO);
 115         /*
 116          * The value FP_1 represents 2^FP_LG, so set the exponent
 117          * there and let normalization fix it up.  Convert negative
 118          * numbers to sign-and-magnitude.  Note that this relies on
 119          * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
 120          */
 121         fp->fp_exp = FP_LG2;
 122         *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i;
 123         fp->fp_mant[2] = 0;
 124         fp->fp_mant[3] = 0;
 125         fpu_norm(fp);
 126         return (FPC_NUM);
 127 }
 128
 129 #define mask(nbits) ((1L << (nbits)) - 1)
 130
 131 /*
 132  * All external floating formats convert to internal in the same manner,
 133  * as defined here.  Note that only normals get an implied 1.0 inserted.
 134  */
 135 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
 136         if (exp == 0) { \
 137                 if (allfrac == 0) \
 138                         return (FPC_ZERO); \
 139                 fp->fp_exp = 1 - expbias; \
 140                 fp->fp_mant[0] = f0; \
 141                 fp->fp_mant[1] = f1; \
 142                 fp->fp_mant[2] = f2; \
 143                 fp->fp_mant[3] = f3; \
 144                 fpu_norm(fp); \
 145                 return (FPC_NUM); \
 146         } \
 147         if (exp == (2 * expbias + 1)) { \
 148                 if (allfrac == 0) \
 149                         return (FPC_INF); \
 150                 fp->fp_mant[0] = f0; \
 151                 fp->fp_mant[1] = f1; \
 152                 fp->fp_mant[2] = f2; \
 153                 fp->fp_mant[3] = f3; \
 154                 return (FPC_QNAN); \
 155         } \
 156         fp->fp_exp = exp - expbias; \
 157         fp->fp_mant[0] = FP_1 | f0; \
 158         fp->fp_mant[1] = f1; \
 159         fp->fp_mant[2] = f2; \
 160         fp->fp_mant[3] = f3; \
 161         return (FPC_NUM)
 162
 163 /*
 164  * 32-bit single precision -> fpn.
 165  * We assume a single occupies at most (64-FP_LG) bits in the internal
 166  * format: i.e., needs at most fp_mant[0] and fp_mant[1].
 167  */
 168 int
 169 fpu_stof(struct fpn *fp, u_int i)
 170 {
 171         int exp;
 172         u_int frac, f0, f1;
 173 #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
 174
 175         exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
 176         frac = i & mask(SNG_FRACBITS);
 177         f0 = frac >> SNG_SHIFT;
 178         f1 = frac << (32 - SNG_SHIFT);
 179         FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
 180 }
 181
 182 /*
 183  * 64-bit double -> fpn.
 184  * We assume this uses at most (96-FP_LG) bits.
 185  */
 186 int
 187 fpu_dtof(struct fpn *fp, u_int i, u_int j)
 188 {
 189         int exp;
 190         u_int frac, f0, f1, f2;
 191 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
 192
 193         exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
 194         frac = i & mask(DBL_FRACBITS - 32);
 195         f0 = frac >> DBL_SHIFT;
 196         f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
 197         f2 = j << (32 - DBL_SHIFT);
 198         frac |= j;
 199         FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
 200 }
 201
 202 /*
 203  * Explode the contents of a register / regpair / regquad.
 204  * If the input is a signalling NaN, an NV (invalid) exception
 205  * will be set.  (Note that nothing but NV can occur until ALU
 206  * operations are performed.)
 207  */
 208 void
 209 fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
 210 {
 211         u_int s, *space;
 212         u_int64_t l, *xspace;
 213
 214         xspace = (u_int64_t *)&fe->fe_fpstate->fpreg[reg];
 215         l = xspace[0];
 216         space = (u_int *)&fe->fe_fpstate->fpreg[reg];
 217         s = space[0];
 218         fp->fp_sign = s >> 31;
 219         fp->fp_sticky = 0;
 220         switch (type) {
 221
 222         case FTYPE_LNG:
 223                 s = fpu_xtof(fp, l);
 224                 break;
 225
 226         case FTYPE_INT:
 227                 s = fpu_itof(fp, space[1]);
 228                 break;
 229
 230         case FTYPE_SNG:
 231                 s = fpu_stof(fp, s);
 232                 break;
 233
 234         case FTYPE_DBL:
 235                 s = fpu_dtof(fp, s, space[1]);
 236                 break;
 237
 238                 panic("fpu_explode");
 239                 panic("fpu_explode: invalid type %d", type);
 240         }
 241
 242         if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
 243                 /*
 244                  * Input is a signalling NaN.  All operations that return
 245                  * an input NaN operand put it through a ``NaN conversion'',
 246                  * which basically just means ``turn on the quiet bit''.
 247                  * We do this here so that all NaNs internally look quiet
 248                  * (we can tell signalling ones by their class).
 249                  */
 250                 fp->fp_mant[0] |= FP_QUIETBIT;
 251                 fe->fe_cx = FPSCR_VXSNAN;       /* assert invalid operand */
 252                 s = FPC_SNAN;
 253         }
 254         fp->fp_class = s;
 255         DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
 256                 ((type == FTYPE_INT) ? 'i' :
 257                         ((type == FTYPE_SNG) ? 's' :
 258                                 ((type == FTYPE_DBL) ? 'd' : '?'))),
 259                 reg));
 260         DUMPFPN(FPE_REG, fp);
 261         DPRINTF(FPE_REG, ("\n"));
 262 }