sys/arch/powerpc/ibm4xx/pci/pci_machdep.c

   1 /*      $NetBSD: pci_machdep.c,v 1.5 2006/06/30 17:54:51 freza Exp $    */
   2
   3 /*
   4  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
   5  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Charles M. Hannum.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Machine-specific functions for PCI autoconfiguration.
  35  *
  36  * On PCs, there are two methods of generating PCI configuration cycles.
  37  * We try to detect the appropriate mechanism for this machine and set
  38  * up a few function pointers to access the correct method directly.
  39  *
  40  * The configuration method can be hard-coded in the config file by
  41  * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
  42  * as defined section 3.6.4.1, `Generating Configuration Cycles'.
  43  */
  44
  45 #include <sys/cdefs.h>
  46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.5 2006/06/30 17:54:51 freza Exp $");
  47
  48 #include <sys/types.h>
  49 #include <sys/param.h>
  50 #include <sys/time.h>
  51 #include <sys/systm.h>
  52 #include <sys/errno.h>
  53 #include <sys/device.h>
  54 #include <sys/extent.h>
  55
  56 #include <uvm/uvm_extern.h>
  57
  58 #include <machine/bus.h>
  59 #include <machine/intr.h>
  60
  61 #include <dev/pci/pcivar.h>
  62 #include <dev/pci/pcireg.h>
  63 #include <dev/pci/pcidevs.h>
  64 #include <dev/pci/pciconf.h>
  65
  66 #include <powerpc/ibm4xx/ibm405gp.h>
  67 #include <powerpc/ibm4xx/dev/pcicreg.h>
  68
  69 static struct powerpc_bus_space pci_iot = {
  70         _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE,
  71         0x00000000,
  72         IBM405GP_PCIC0_BASE,            /* extent base */
  73         IBM405GP_PCIC0_BASE + 8,        /* extent limit */
  74 };
  75
  76 static bus_space_handle_t pci_ioh;
  77
  78 void
  79 pci_machdep_init(void)
  80 {
  81
  82         if (pci_ioh == 0 &&
  83            (bus_space_init(&pci_iot, "pcicfg", NULL, 0) ||
  84             bus_space_map(&pci_iot, IBM405GP_PCIC0_BASE, 8, 0, &pci_ioh)))
  85                 panic("Cannot map PCI registers");
  86 }
  87
  88 void
  89 pci_attach_hook(struct device *parent, struct device *self,
  90                 struct pcibus_attach_args *pba)
  91 {
  92
  93 #ifdef PCI_CONFIGURE_VERBOSE
  94         printf("pci_attach_hook\n");
  95         ibm4xx_show_pci_map();
  96 #endif
  97         ibm4xx_setup_pci();
  98 #ifdef PCI_CONFIGURE_VERBOSE
  99         ibm4xx_show_pci_map();
 100 #endif
 101 }
 102
 103 int
 104 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
 105 {
 106
 107         /*
 108          * Bus number is irrelevant.  Configuration Mechanism 1 is in
 109          * use, can have devices 0-32 (i.e. the `normal' range).
 110          */
 111         return 31;
 112 }
 113
 114 pcitag_t
 115 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
 116 {
 117         pcitag_t tag;
 118
 119         if (bus >= 256 || device >= 32 || function >= 8)
 120                 panic("pci_make_tag: bad request");
 121
 122         /* XXX magic number */
 123         tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8);
 124
 125         return tag;
 126 }
 127
 128 void
 129 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
 130 {
 131
 132         if (bp != NULL)
 133                 *bp = (tag >> 16) & 0xff;
 134         if (dp != NULL)
 135                 *dp = (tag >> 11) & 0x1f;
 136         if (fp != NULL)
 137                 *fp = (tag >> 8) & 0x07;
 138 }
 139
 140 pcireg_t
 141 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
 142 {
 143         pcireg_t data;
 144
 145         /* 405GT BIOS disables interrupts here. Should we? --Art */
 146         bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);
 147         data = bus_space_read_4(&pci_iot, pci_ioh, PCIC_CFGDATA);
 148         /* 405GP pass2 errata #6 */
 149         bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0);
 150         return data;
 151 }
 152
 153 void
 154 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
 155 {
 156
 157         bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);
 158         bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGDATA, data);
 159         /* 405GP pass2 errata #6 */
 160         bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0);
 161 }
 162
 163 const char *
 164 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
 165 {
 166         static char irqstr[8];          /* 4 + 2 + NUL + sanity */
 167
 168         /* Make sure it looks sane, intr_establish does the real check. */
 169         if (ih < 0 || ih > 99)
 170                 panic("pci_intr_string: handle %d won't fit two digits", ih);
 171
 172         sprintf(irqstr, "irq %d", ih);
 173         return (irqstr);
 174
 175 }
 176
 177 const struct evcnt *
 178 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
 179 {
 180
 181         /* XXX for now, no evcnt parent reported */
 182         return NULL;
 183 }
 184
 185 int
 186 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
 187                  int attr, uint64_t data)
 188 {
 189
 190         switch (attr) {
 191         case PCI_INTR_MPSAFE:
 192                 return 0;
 193         default:
 194                 return ENODEV;
 195         }
 196 }
 197
 198 void *
 199 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
 200                    int (*func)(void *), void *arg)
 201 {
 202         return intr_establish(ih, IST_LEVEL, level, func, arg);
 203 }
 204
 205 void
 206 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
 207 {
 208
 209         intr_disestablish(cookie);
 210 }
 211
 212 /* Avoid overconfiguration */
 213 int
 214 pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
 215 {
 216
 217         if ((PCI_VENDOR(id) == PCI_VENDOR_IBM && PCI_PRODUCT(id) == PCI_PRODUCT_IBM_405GP) ||
 218             (PCI_VENDOR(id) == PCI_VENDOR_INTEL && PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_80960_RP)) {
 219                 /* Don't configure the bridge and PCI probe. */
 220                 return 0;
 221         }
 222         return PCI_CONF_DEFAULT;
 223 }