sys/arch/sparc/dev/cgfourteenreg.h

   1 /*      $NetBSD: cgfourteenreg.h,v 1.3.36.1 2007/10/03 19:25:10 garbled Exp $ */
   2
   3 /*
   4  * Copyright (c) 1996
   5  *      The President and Fellows of Harvard College. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Harvard University and
  18  *      its contributors.
  19  * 4. Neither the name of the University nor the names of its contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  */
  35
  36 /*
  37  * Register/dac/clut/cursor definitions for cgfourteen frame buffer
  38  */
  39
  40 /* Locations of control registers in cg14 register set */
  41 #define CG14_OFFSET_CURS        0x1000
  42 #define CG14_OFFSET_DAC         0x2000
  43 #define CG14_OFFSET_XLUT        0x3000
  44 #define CG14_OFFSET_CLUT1       0x4000
  45 #define CG14_OFFSET_CLUT2       0x5000
  46 #define CG14_OFFSET_CLUT3       0x6000
  47 #define CG14_OFFSET_CLUTINCR    0xf000
  48
  49 /* cursor registers */
  50 #define CG14_CURSOR_PLANE0      0x1000
  51 #define CG14_CURSOR_PLANE1      0x1080
  52 #define CG14_CURSOR_CONTROL     0x1100
  53         #define CG14_CRSR_ENABLE        0x04
  54         #define CG14_CRSR_DBLBUFFER     0x02
  55 #define CG14_CURSOR_X           0x1104
  56 #define CG14_CURSOR_Y           0x1106
  57 #define CG14_CURSOR_COLOR1      0x1108
  58 #define CG14_CURSOR_COLOR2      0x110c
  59 #define CG14_CURSOR_COLOR3      0x1110
  60
  61 /* ranges in framebuffer space */
  62 #define CG14_FB_VRAM            0x00000000
  63 #define CG14_FB_CBGR            0x01000000
  64 #define CG14_FB_PX32            0x03000000
  65 #define CG14_FB_PG32            0x03800000
  66
  67 /* Main control register set */
  68 struct cg14ctl {
  69         volatile uint8_t        ctl_mctl;       /* main control register */
  70 #define CG14_MCTL       0x00000000
  71 #define CG14_MCTL_ENABLEINTR    0x80            /* interrupts */
  72 #define CG14_MCTL_ENABLEVID     0x40            /* enable video */
  73 #define CG14_MCTL_PIXMODE_MASK  0x30
  74 #define         CG14_MCTL_PIXMODE_8     0x00    /* data is 16 8-bit pixels */
  75 #define         CG14_MCTL_PIXMODE_16    0x20    /* data is 8 16-bit pixels */
  76 #define         CG14_MCTL_PIXMODE_32    0x30    /* data is 4 32-bit pixels */
  77 #define CG14_MCTL_PIXMODE_SHIFT 4
  78 #define CG14_MCTL_TMR           0x0c
  79 #define CG14_MCTL_ENABLETMR     0x02
  80 #define CG14_MCTL_rev0RESET     0x01
  81 #define CG14_MCTL_POWERCTL      0x01
  82
  83         volatile uint8_t        ctl_ppr;        /* packed pixel register */
  84         volatile uint8_t        ctl_tmsr0;      /* test status reg. 0 */
  85         volatile uint8_t        ctl_tmsr1;      /* test status reg. 1 */
  86         volatile uint8_t        ctl_msr;        /* master status register */
  87         volatile uint8_t        ctl_fsr;        /* fault status register */
  88         volatile uint8_t        ctl_rsr;        /* revision status register */
  89 #define CG14_RSR_REVMASK        0xf0            /*  mask to get revision */
  90 #define CG14_RSR_IMPLMASK       0x0f            /*  mask to get impl. code */
  91         volatile uint8_t        ctl_ccr;        /* clock control register */
  92         /* XXX etc. */
  93 };
  94
  95 /* Hardware cursor map */
  96 #define CG14_CURS_SIZE          32
  97 struct cg14curs {
  98         volatile uint32_t       curs_plane0[CG14_CURS_SIZE];    /* plane 0 */
  99         volatile uint32_t       curs_plane1[CG14_CURS_SIZE];
 100         volatile uint8_t        curs_ctl;       /* control register */
 101 #define CG14_CURS_ENABLE        0x4
 102 #define CG14_CURS_DOUBLEBUFFER  0x2             /* use X-channel for curs */
 103         volatile uint8_t        pad0[3];
 104         volatile uint16_t       curs_x;         /* x position */
 105         volatile uint16_t       curs_y;         /* y position */
 106         volatile uint32_t       curs_color1;    /* color register 1 */
 107         volatile uint32_t       curs_color2;    /* color register 2 */
 108         volatile uint32_t       pad[444];       /* pad to 2KB boundary */
 109         volatile uint32_t       curs_plane0incr[CG14_CURS_SIZE]; /* autoincr */
 110         volatile uint32_t       curs_plane1incr[CG14_CURS_SIZE]; /* autoincr */
 111 };
 112
 113 /* DAC */
 114 struct cg14dac {
 115         volatile uint8_t        dac_addr;       /* address register */
 116         volatile uint8_t        pad0[255];
 117         volatile uint8_t        dac_gammalut;   /* gamma LUT */
 118         volatile uint8_t        pad1[255];
 119         volatile uint8_t        dac_regsel;     /* register select */
 120         volatile uint8_t        pad2[255];
 121         volatile uint8_t        dac_mode;       /* mode register */
 122 };
 123
 124 #define CG14_CLUT_SIZE  256
 125
 126 /* XLUT registers */
 127 struct cg14xlut {
 128         volatile uint8_t        xlut_lut[CG14_CLUT_SIZE];       /* the LUT */
 129         volatile uint8_t        xlut_lutd[CG14_CLUT_SIZE];      /* ??? */
 130         volatile uint8_t        pad0[0x600];
 131         volatile uint8_t        xlut_lutinc[CG14_CLUT_SIZE];    /* autoincrLUT*/
 132         volatile uint8_t        xlut_lutincd[CG14_CLUT_SIZE];
 133 };
 134
 135 /* Color Look-Up Table (CLUT) */
 136 struct cg14clut {
 137         volatile uint32_t       clut_lut[CG14_CLUT_SIZE];       /* the LUT */
 138         volatile uint32_t       clut_lutd[CG14_CLUT_SIZE];      /* ??? */
 139         volatile uint32_t       clut_lutinc[CG14_CLUT_SIZE];    /* autoincr */
 140         volatile uint32_t       clut_lutincd[CG14_CLUT_SIZE];
 141 };