sys/arch/sparc/dev/sbusreg.h

   1 /*      $NetBSD: sbusreg.h,v 1.5 2003/08/07 16:29:36 agc Exp $ */
   2
   3 /*
   4  * Copyright (c) 1992, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This software was developed by the Computer Systems Engineering group
   8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
   9  * contributed to Berkeley.
  10  *
  11  * All advertising materials mentioning features or use of this software
  12  * must display the following acknowledgement:
  13  *      This product includes software developed by the University of
  14  *      California, Lawrence Berkeley Laboratory.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  * 3. Neither the name of the University nor the names of its contributors
  25  *    may be used to endorse or promote products derived from this software
  26  *    without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  *      @(#)sbusreg.h   8.1 (Berkeley) 6/11/93
  41  */
  42
  43 /*
  44  * Sun-4c S-bus definitions.  (Should be made generic!)
  45  *
  46  * Sbus slot 0 is not a separate slot; it talks to the onboard I/O devices.
  47  * It is, however, addressed just like any `real' Sbus.
  48  *
  49  * Sbus device addresses are obtained from the FORTH PROMs.  They come
  50  * in `absolute' and `relative' address flavors, so we have to handle both.
  51  * Relative addresses do *not* include the slot number.
  52  */
  53 #define SBUS_BASE               0xf8000000
  54 #define SBUS_ADDR(slot, off)    (SBUS_BASE + ((slot) << 25) + (off))
  55 #define SBUS_ABS(a)             ((unsigned)(a) >= SBUS_BASE)
  56 #define SBUS_ABS_TO_SLOT(a)     (((a) - SBUS_BASE) >> 25)
  57 #define SBUS_ABS_TO_OFFSET(a)   (((a) - SBUS_BASE) & 0x1ffffff)
  58
  59 #if _sbus_for_your_eyes_only_
  60 struct sbusreg {
  61         uint32_t        sbus_afsr;      /* M-to-S Asynchronous Fault Status */
  62         uint32_t        sbus_afar;      /* M-to-S Asynchronous Fault Address */
  63         uint32_t        sbus_arbiter;   /* Arbiter Enable  */
  64         uint32_t        sbus_reserved1;
  65
  66 #define NSBUSCFG        20
  67         /* Actual number dependent on machine model */
  68         uint32_t        sbus_sbuscfg[NSBUSCFG]; /* Sbus configuration control */
  69 };
  70 #endif
  71
  72 /* Register offsets */
  73 #define SBUS_AFSR_REG   0
  74 #define SBUS_AFAR_REG   4
  75 #define SBUS_ARB_REG    8
  76 #define SBUS_CFG_REG(n) (16 + 4*(n))
  77 #define SBUS_MFSR_REG   32              /* MS1 only: memory fault status */
  78 #define SBUS_MFAR_REG   34              /* MS1 only: memory fault address */
  79
  80 /* M-to-S Asynchronous Fault Status register */
  81 #define SBUS_AFSR_PAH   0x0000000f      /* PA<35:32> of fault address */
  82 #define SBUS_AFSR_WM    0x00000100      /* SBus wide mode access */
  83 #define SBUS_AFSR_SSIZ  0x00000e00      /* Size of error transaction */
  84 #define SBUS_AFSR_SA    0x0001f000      /* bits <4:0> of fault address */
  85 #define SBUS_AFSR_FAV   0x00020000      /* Fault address valid (MS only) */
  86 #define SBUS_AFSR_RD    0x00040000      /* Read transaction */
  87 #define SBUS_AFSR_ME    0x00080000      /* Multiple error */
  88 #define SBUS_AFSR_MID   0x00f00000      /* Module ID */
  89 #define SBUS_AFSR_S     0x01000000      /* Supervisor mode */
  90 #define SBUS_AFSR_SIZ   0x0e000000      /* Requested transaction size */
  91 #define SBUS_AFSR_BERR  0x10000000      /* Bus error (Sbus) or error ACK (VME)*/
  92 #define SBUS_AFSR_TO    0x20000000      /* Bus Timeout */
  93 #define SBUS_AFSR_LE    0x40000000      /* SBus late error */
  94 #define SBUS_AFSR_ERR   0x80000000      /* Summary bit: one of LE,TO,BERR */
  95 #define SBUS_AFSR_BITS  "\177\020"                                      \
  96                         "f\0\4PAH\0b\10WM\0f\11\3SSIZ\0f\14\5SA\0"      \
  97                         "b\11FAV\0b\12RD\0b\13ME\0f\14\4MID\0b\30S\0"   \
  98                         "f\31\3SIZ\0b\34BERR\0b\35TO\0b\36LE\0b\37ERR\0"
  99
 100 /* Arbiter Enable register */
 101 #define SBUS_ARB_P1     0x00000002      /* Enable MBus master 9 */
 102 #define SBUS_ARB_P2     0x00000004      /* Enable MBus master 10 */
 103 #define SBUS_ARB_P3     0x00000008      /* Enable MBus master 11 */
 104 #define SBUS_ARB_B0     0x00010000      /* Enable SBus Slot 0 */
 105 #define SBUS_ARB_B1     0x00020000      /* Enable SBus Slot 1 */
 106 #define SBUS_ARB_B2     0x00040000      /* Enable SBus Slot 2 */
 107 #define SBUS_ARB_B3     0x00080000      /* Enable SBus Slot 3 */
 108 #define SBUS_ARB_BF     0x00100000      /* Enable on-board SBus devices */
 109 #define SBUS_ARB_SBW    0x80000000      /* Enable S-to-M synchronous writes */
 110 #define SBUS_ARB_BITS   "\177\020"                      \
 111                         "f\0\4CPUs Enabled\0"           \
 112                         "f\20\5SBus Slots Enabled\0"    \
 113                         "b\37S-to-M synchronous\0"
 114
 115 /* SBus Slot Configuration register */
 116 #define SBUS_CFG_BY     0x00000001      /* Bypass Enabled */
 117 #define SBUS_CFG_BA8    0x00000002      /* Slave supports 8-byte bursts */
 118 #define SBUS_CFG_BA16   0x00000004      /* Slave supports 16-byte bursts */
 119 #define SBUS_CFG_BA32   0x00000008      /* Slave supports 32-byte bursts */
 120 #define SBUS_CFG_BA64   0x00000010      /* Slave supports 64-byte bursts */
 121 #define SBUS_CFG_WMA    0x00004000      /* Enable wide-mode access */
 122 #define SBUS_CFG_CP     0x00008000      /* Cacheable bit */
 123 #define SBUS_CFG_SEGA   0x003f0000      /* PA<35:30> in by-pass mode */
 124 #define SBUS_CFG_BITS   "\177\020"                                      \
 125                         "b\0BY\0b\1BA8\0b\2BA16\0b\3BA32\0b\4BA64\0"    \
 126                         "b\16WMA\0b\17CP\0f\20\6SEGA\0"