sys/arch/sparc/fpu/fpu_emu.h

   1 /*      $NetBSD: fpu_emu.h,v 1.5.16.3 2004/09/21 13:22:14 skrll Exp $ */
   2
   3 /*
   4  * Copyright (c) 1992, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This software was developed by the Computer Systems Engineering group
   8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
   9  * contributed to Berkeley.
  10  *
  11  * All advertising materials mentioning features or use of this software
  12  * must display the following acknowledgement:
  13  *      This product includes software developed by the University of
  14  *      California, Lawrence Berkeley Laboratory.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  * 3. Neither the name of the University nor the names of its contributors
  25  *    may be used to endorse or promote products derived from this software
  26  *    without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  *      @(#)fpu_emu.h   8.1 (Berkeley) 6/11/93
  41  */
  42
  43 #if defined(_KERNEL_OPT)
  44 #include "opt_sparc_arch.h"
  45 #endif
  46
  47 /*
  48  * Floating point emulator (tailored for SPARC, but structurally
  49  * machine-independent).
  50  *
  51  * Floating point numbers are carried around internally in an `expanded'
  52  * or `unpacked' form consisting of:
  53  *      - sign
  54  *      - unbiased exponent
  55  *      - mantissa (`1.' + 112-bit fraction + guard + round)
  56  *      - sticky bit
  57  * Any implied `1' bit is inserted, giving a 113-bit mantissa that is
  58  * always nonzero.  Additional low-order `guard' and `round' bits are
  59  * scrunched in, making the entire mantissa 115 bits long.  This is divided
  60  * into four 32-bit words, with `spare' bits left over in the upper part
  61  * of the top word (the high bits of fp_mant[0]).  An internal `exploded'
  62  * number is thus kept within the half-open interval [1.0,2.0) (but see
  63  * the `number classes' below).  This holds even for denormalized numbers:
  64  * when we explode an external denorm, we normalize it, introducing low-order
  65  * zero bits, so that the rest of the code always sees normalized values.
  66  *
  67  * Note that a number of our algorithms use the `spare' bits at the top.
  68  * The most demanding algorithm---the one for sqrt---depends on two such
  69  * bits, so that it can represent values up to (but not including) 8.0,
  70  * and then it needs a carry on top of that, so that we need three `spares'.
  71  *
  72  * The sticky-word is 32 bits so that we can use `OR' operators to goosh
  73  * whole words from the mantissa into it.
  74  *
  75  * All operations are done in this internal extended precision.  According
  76  * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is,
  77  * it is OK to do a+b in extended precision and then round the result to
  78  * single precision---provided single, double, and extended precisions are
  79  * `far enough apart' (they always are), but we will try to avoid any such
  80  * extra work where possible.
  81  */
  82 struct fpn {
  83         int     fp_class;               /* see below */
  84         int     fp_sign;                /* 0 => positive, 1 => negative */
  85         int     fp_exp;                 /* exponent (unbiased) */
  86         int     fp_sticky;              /* nonzero bits lost at right end */
  87         u_int   fp_mant[4];             /* 115-bit mantissa */
  88 };
  89
  90 #define FP_NMANT        115             /* total bits in mantissa (incl g,r) */
  91 #define FP_NG           2               /* number of low-order guard bits */
  92 #define FP_LG           ((FP_NMANT - 1) & 31)   /* log2(1.0) for fp_mant[0] */
  93 #define FP_LG2          ((FP_NMANT - 1) & 63)   /* log2(1.0) for fp_mant[0] and fp_mant[1] */
  94 #define FP_QUIETBIT     (1 << (FP_LG - 1))      /* Quiet bit in NaNs (0.5) */
  95 #define FP_1            (1 << FP_LG)            /* 1.0 in fp_mant[0] */
  96 #define FP_2            (1 << (FP_LG + 1))      /* 2.0 in fp_mant[0] */
  97
  98 /*
  99  * Number classes.  Since zero, Inf, and NaN cannot be represented using
 100  * the above layout, we distinguish these from other numbers via a class.
 101  * In addition, to make computation easier and to follow Appendix N of
 102  * the SPARC Version 8 standard, we give each kind of NaN a separate class.
 103  */
 104 #define FPC_SNAN        -2              /* signalling NaN (sign irrelevant) */
 105 #define FPC_QNAN        -1              /* quiet NaN (sign irrelevant) */
 106 #define FPC_ZERO        0               /* zero (sign matters) */
 107 #define FPC_NUM         1               /* number (sign matters) */
 108 #define FPC_INF         2               /* infinity (sign matters) */
 109
 110 #define ISNAN(fp)       ((fp)->fp_class < 0)
 111 #define ISZERO(fp)      ((fp)->fp_class == 0)
 112 #define ISINF(fp)       ((fp)->fp_class == FPC_INF)
 113
 114 /*
 115  * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points
 116  * to the `more significant' operand for our purposes.  Appendix N says that
 117  * the result of a computation involving two numbers are:
 118  *
 119  *      If both are SNaN: operand 2, converted to Quiet
 120  *      If only one is SNaN: the SNaN operand, converted to Quiet
 121  *      If both are QNaN: operand 2
 122  *      If only one is QNaN: the QNaN operand
 123  *
 124  * In addition, in operations with an Inf operand, the result is usually
 125  * Inf.  The class numbers are carefully arranged so that if
 126  *      (unsigned)class(op1) > (unsigned)class(op2)
 127  * then op1 is the one we want; otherwise op2 is the one we want.
 128  */
 129 #define ORDER(x, y) { \
 130         if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \
 131                 SWAP(x, y); \
 132 }
 133 #define SWAP(x, y) { \
 134         register struct fpn *swap; \
 135         swap = (x), (x) = (y), (y) = swap; \
 136 }
 137
 138 /*
 139  * Emulator state.
 140  */
 141 struct fpemu {
 142 #ifndef SUN4U
 143         struct  fpstate *fe_fpstate;    /* registers, etc */
 144 #else /* SUN4U */
 145         struct  fpstate64 *fe_fpstate;  /* registers, etc */
 146 #endif /* SUN4U */
 147         int     fe_fsr;                 /* fsr copy (modified during op) */
 148         int     fe_cx;                  /* exceptions */
 149         struct  fpn fe_f1;              /* operand 1 */
 150         struct  fpn fe_f2;              /* operand 2, if required */
 151         struct  fpn fe_f3;              /* available storage for result */
 152 };
 153
 154 /*
 155  * Arithmetic functions.
 156  * Each of these may modify its inputs (f1,f2) and/or the temporary.
 157  * Each returns a pointer to the result and/or sets exceptions.
 158  */
 159 struct  fpn *fpu_add(struct fpemu *);
 160 #define fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, fpu_add(fe))
 161 struct  fpn *fpu_mul(struct fpemu *);
 162 struct  fpn *fpu_div(struct fpemu *);
 163 struct  fpn *fpu_sqrt(struct fpemu *);
 164
 165 /*
 166  * Other functions.
 167  */
 168
 169 /* Perform a compare instruction (with or without unordered exception). */
 170 void    fpu_compare(struct fpemu *, int);
 171
 172 /* Build a new Quiet NaN (sign=0, frac=all 1's). */
 173 struct  fpn *fpu_newnan(struct fpemu *);
 174
 175 /*
 176  * Shift a number right some number of bits, taking care of round/sticky.
 177  * Note that the result is probably not a well-formed number (it will lack
 178  * the normal 1-bit mant[0]&FP_1).
 179  */
 180 int     fpu_shr(struct fpn *, int);
 181
 182 void    fpu_explode(struct fpemu *, struct fpn *, int, int);
 183 void    fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
 184
 185 #ifdef DEBUG
 186 #define FPE_INSN        0x1
 187 #define FPE_REG         0x2
 188 extern int fpe_debug;
 189 void    fpu_dumpfpn(struct fpn *);
 190 #define DPRINTF(x, y)   if (fpe_debug & (x)) printf y
 191 #define DUMPFPN(x, f)   if (fpe_debug & (x)) fpu_dumpfpn((f))
 192 #else
 193 #define DPRINTF(x, y)
 194 #define DUMPFPN(x, f)
 195 #endif