sys/arch/sparc64/dev/iommureg.h

   1 /*      $NetBSD: iommureg.h,v 1.14 2006/02/13 21:47:12 cdi Exp $        */
   2
   3 /*
   4  * Copyright (c) 1992, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This software was developed by the Computer Systems Engineering group
   8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
   9  * contributed to Berkeley.
  10  *
  11  * All advertising materials mentioning features or use of this software
  12  * must display the following acknowledgement:
  13  *      This product includes software developed by the University of
  14  *      California, Lawrence Berkeley Laboratory.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  * 3. Neither the name of the University nor the names of its contributors
  25  *    may be used to endorse or promote products derived from this software
  26  *    without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  *      @(#)sbusreg.h   8.1 (Berkeley) 6/11/93
  41  */
  42
  43 #ifndef _SPARC64_DEV_IOMMUREG_H_
  44 #define _SPARC64_DEV_IOMMUREG_H_
  45
  46 /*
  47  * UltraSPARC IOMMU registers, common to both the sbus and PCI
  48  * controllers.
  49  */
  50
  51 /* iommmu registers */
  52 struct iommureg {
  53         uint64_t        iommu_cr;       /* IOMMU control register */
  54         uint64_t        iommu_tsb;      /* IOMMU TSB base register */
  55         uint64_t        iommu_flush;    /* IOMMU flush register */
  56 };
  57
  58 /* streaming buffer registers */
  59 struct iommu_strbuf {
  60         uint64_t        strbuf_ctl;     /* streaming buffer control reg */
  61         uint64_t        strbuf_pgflush; /* streaming buffer page flush */
  62         uint64_t        strbuf_flushsync;/* streaming buffer flush sync */
  63 };
  64
  65 #define IOMMUREG(x)     (offsetof(struct iommureg, x))
  66 #define STRBUFREG(x)    (offsetof(struct iommu_strbuf, x))
  67 /* streaming buffer control register */
  68 #define STRBUF_EN       0x000000000000000001LL
  69 #define STRBUF_D        0x000000000000000002LL
  70
  71 /* control register bits */
  72 #define IOMMUCR_TSB1K           0x000000000000000000LL  /* Nummber of entries in IOTSB */
  73 #define IOMMUCR_TSB2K           0x000000000000010000LL
  74 #define IOMMUCR_TSB4K           0x000000000000020000LL
  75 #define IOMMUCR_TSB8K           0x000000000000030000LL
  76 #define IOMMUCR_TSB16K          0x000000000000040000LL
  77 #define IOMMUCR_TSB32K          0x000000000000050000LL
  78 #define IOMMUCR_TSB64K          0x000000000000060000LL
  79 #define IOMMUCR_TSB128K         0x000000000000070000LL
  80 #define IOMMUCR_TSBMASK         0xfffffffffffff8ffffLL  /* Mask for above */
  81 #define IOMMUCR_8KPG            0x000000000000000000LL  /* 8K iommu page size */
  82 #define IOMMUCR_64KPG           0x000000000000000004LL  /* 64K iommu page size */
  83 #define IOMMUCR_DE              0x000000000000000002LL  /* Diag enable */
  84 #define IOMMUCR_EN              0x000000000000000001LL  /* Enable IOMMU */
  85
  86 /*
  87  * IOMMU stuff
  88  */
  89 #define IOTTE_V         0x8000000000000000LL    /* Entry valid */
  90 #define IOTTE_64K       0x2000000000000000LL    /* 8K or 64K page? */
  91 #define IOTTE_8K        0x0000000000000000LL
  92 #define IOTTE_STREAM    0x1000000000000000LL    /* Is page streamable? */
  93 #define IOTTE_LOCAL     0x0800000000000000LL    /* Accesses to same bus segment? */
  94 #define IOTTE_PAMASK    0x000001ffffffe000LL    /* Let's assume this is correct */
  95 #define IOTTE_C         0x0000000000000010LL    /* Accesses to cacheable space */
  96 #define IOTTE_W         0x0000000000000002LL    /* Writable */
  97
  98 /*
  99  * On sun4u each bus controller has a separate IOMMU.  The IOMMU has
 100  * a TSB which must be page aligned and physically contiguous.  Mappings
 101  * can be of 8K IOMMU pages or 64K IOMMU pages.  We use 8K for compatibility
 102  * with the CPU's MMU.
 103  *
 104  * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
 105  * following size segments:
 106  *
 107  *      VA size         VA base         TSB size        tsbsize
 108  *      --------        --------        ---------       -------
 109  *      8MB             ff800000        8K              0
 110  *      16MB            ff000000        16K             1
 111  *      32MB            fe000000        32K             2
 112  *      64MB            fc000000        64K             3
 113  *      128MB           f8000000        128K            4
 114  *      256MB           f0000000        256K            5
 115  *      512MB           e0000000        512K            6
 116  *      1GB             c0000000        1MB             7
 117  *
 118  * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
 119  * this scheme to determine the IOVA base address.  Instead, bits 31-29 are
 120  * used to check against the Target Address Space register in the IIi and
 121  * the IOMMU is used if they hit.  God knows what goes on in the IIe.
 122  *
 123  */
 124
 125
 126 #define IOTSB_VEND              (u_int)(0xffffffffffffffffLL<<PGSHIFT)
 127 #define IOTSB_VSTART(sz)        (u_int)(IOTSB_VEND << ((sz)+10))
 128 #define IOTSB_VSIZE(sz)         (u_int)(1 << ((sz)+10+PGSHIFT))
 129
 130 #define MAKEIOTTE(pa,w,c,s)     (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K))
 131 #define IOTSBSLOT(va,sz)        ((u_int)(((vaddr_t)(va))-(is->is_dvmabase))>>PGSHIFT)
 132
 133 /*
 134  * interrupt map stuff.  this belongs elsewhere.
 135  */
 136
 137 #define INTMAP_V        0x080000000LL   /* Interrupt valid (enabled) */
 138 #define INTMAP_TID      0x07c000000LL   /* UPA target ID mask */
 139 #define INTMAP_TID_SHIFT 26
 140 #define INTMAP_IGN      0x0000007c0LL   /* Interrupt group no (sbus only). */
 141 #define INTMAP_IGN_SHIFT 6
 142 #define INTMAP_INO      0x00000003fLL   /* Interrupt number */
 143 #define INTMAP_INR      (INTMAP_IGN|INTMAP_INO)
 144 #define INTMAP_SBUSSLOT 0x000000018LL   /* SBUS slot # */
 145 #define INTMAP_PCIBUS   0x000000010LL   /* PCI bus number (A or B) */
 146 #define INTMAP_PCISLOT  0x00000000cLL   /* PCI slot # */
 147 #define INTMAP_PCIINT   0x000000003LL   /* PCI interrupt #A,#B,#C,#D */
 148 #define INTMAP_OBIO     0x000000020LL   /* Onboard device */
 149 #define INTMAP_LSHIFT   11              /* Encode level in vector */
 150 #define INTLEVENCODE(x) (((x)&0x0f)<<INTMAP_LSHIFT)
 151 #define INTLEV(x)       (((x)>>INTMAP_LSHIFT)&0x0f)
 152 #define INTVEC(x)       ((x)&INTMAP_INR)
 153 #define INTSLOT(x)      (((x)>>3)&0x7)
 154 #define INTPRI(x)       ((x)&0x7)
 155 #define INTINO(x)       ((x)&INTMAP_INO)
 156 #define INTIGN(x)       ((x)&INTMAP_IGN)
 157
 158 #define INTPCI_MAXOBINO 0x16            /* maximum OBIO INO value for PCI */
 159 #define INTPCIOBINOX(x) ((x)&0x1f)      /* OBIO ino index (for PCI machines) */
 160 #define INTPCIINOX(x)   (((x)&0x1c)>>2) /* PCI ino index */
 161
 162 #endif /* _SPARC64_DEV_IOMMUREG_H_ */