sys/arch/sparc64/dev/psmreg.h

   1 /*
   2  * Copyright (c) 2006 Itronix Inc.
   3  * All rights reserved.
   4  *
   5  * Ported from Tadpole Solaris sources by Garrett D'Amore for Itronix Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of Itronix Inc. may not be used to endorse
  16  *    or promote products derived from this software without specific
  17  *    prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Copyright (c) 2002 by Tadpole Technology
  34  */
  35
  36 #ifndef PSM_H
  37 #define PSM_H
  38
  39 #define PSM_PRDL        0x00    /* Posted read data low byte */
  40 #define PSM_PRDU        0x01    /* Posted read data high byte */
  41 #define PSM_ISR         0x02    /* Interrupt status register */
  42 #define PSM_STAT        0x03    /* Status register */
  43 #define PSM_PSR0        0x04    /* Programmable status register #0 */
  44 #define PSM_PSR1        0x05    /* Programmable status register #1 */
  45 #define PSM_PSR2        0x06    /* Programmable status register #2 */
  46 #define PSM_PSR3        0x07    /* Programmable status register #3 */
  47
  48 #define PSM_PWDL        0x00    /* Posted write data low byte */
  49 #define PSM_PWDU        0x01    /* Posted write data high byte */
  50 #define PSM_IAR         0x02    /* Indirect access register */
  51 #define PSM_CMR         0x03    /* Command mode register */
  52 #define PSM_RSV1        0x04    /* Reserved */
  53 #define PSM_ICR         0x05    /* Interrupt clear register */
  54 #define PSM_RSV2        0x06    /* Reserved */
  55 #define PSM_MCR         0x07    /* Master command register */
  56
  57 /* Interrupt status register defenitions */
  58
  59 #define PSM_ISR_PO      0x01    /* Power switch activated */
  60 #define PSM_ISR_DK      0x02    /* System has been docked */
  61 #define PSM_ISR_UDK     0x04    /* System has been un-docked */
  62 #define PSM_ISR_LIDO    0x08    /* Transition to clamshell closed */
  63 #define PSM_ISR_LIDC    0x10    /* Transition to clamshell open */
  64 #define PSM_ISR_TMP     0x20    /* Over temperature condition detected */
  65 #define PSM_ISR_BCC     0x40    /* Battery configuration changed */
  66 #define PSM_ISR_RPD     0x80    /* Request to power down */
  67
  68 /* Status registert defenitions */
  69
  70 #define PSM_STAT_AC     0x01    /* Operating under AC power */
  71 #define PSM_STAT_OVT    0x02    /* Over temperature condition */
  72 #define PSM_STAT_UN1    0x04    /* Unused */
  73 #define PSM_STAT_UN2    0x08    /* Unused */
  74 #define PSM_STAT_ERR    0x10    /* Hardware error occured */
  75 #define PSM_STAT_MCR    0x20    /* Master Command Register busy */
  76 #define PSM_STAT_WBF    0x40    /* Write buffer full */
  77 #define PSM_STAT_RDA    0x80    /* Read data available */
  78
  79 /* Command Mode Register defenitions */
  80
  81 #define PSM_CMR_DATA(m,l,d,ra)  (ra & 0x07) | \
  82                                 ((d & 0x01) << 3) | \
  83                                 ((l & 0x01) << 4) | \
  84                                 ((m & 0x07) << 5)
  85
  86 #define PSM_MODE_SYSCFG 0x00    /* System configuration mode */
  87 #define PSM_MODE_BQRW   0x01    /* Read write battery fuel guage */
  88 #define PSM_MODE_BCB    0x02    /* Battery status block control */
  89 #define PSM_MODE_PMPS   0x03    /* Power management policies/status */
  90 #define PSM_MODE_MISC   0x04    /* Misc. control / status registers */
  91 #define PSM_MODE_I2C    0x05    /* Direct I2C control */
  92 #define PSM_MODE_UN1    0x06    /* Unused */
  93 #define PSM_MODE_UN2    0x07    /* Unused */
  94
  95 #define PSM_L_8         0x00
  96 #define PSM_L_16        0x01
  97
  98 #define PSM_D_WR        0x00
  99 #define PSM_D_RD        0x01
 100
 101 /* Master Command Register defenitions */
 102
 103 #define PSM_MCR_NA1     0x01    /* Not available */
 104 #define PSM_MCR_NA2     0x02    /* Not available */
 105 #define PSM_MCR_NA3     0x04    /* Not available */
 106 #define PSM_MCR_AUTO    0x08    /* Enable active battery management */
 107 #define PSM_MCR_SD      0x10    /* Shutdown permission granted */
 108 #define PSM_MCR_MON     0x20    /* Monitor motherboard interrupts/dma */
 109 #define PSM_MCR_OBP     0x40    /* OBP done notification */
 110 #define PSM_MCR_RST     0x80    /* Reset PSMbus interface */
 111
 112 /* Mode dependant registers */
 113
 114 /* Mode 0 - System configuration */
 115
 116 #define PSM_SYSCFG_PSSR0        0x00
 117 #define PSM_SYSCFG_PSCR0        0x01
 118 #define PSM_SYSCFG_PSSR1        0x02
 119 #define PSM_SYSCFG_PSCR1        0x03
 120 #define PSM_SYSCFG_PSSR2        0x04
 121 #define PSM_SYSCFG_PSCR2        0x05
 122 #define PSM_SYSCFG_PSSR3        0x06
 123 #define PSM_SYSCFG_PSCR3        0x07
 124
 125 #define PSM_SYSCFG_PSSR(batt,fgr)       (fgr & 0x1f ) | \
 126                                         ((batt & 0x07) << 5)
 127
 128 #define PSM_SYSCFG_PSCR(e,lo,ti)        (ti & 0x0f) | \
 129                                         ((lo & 0x01) << 6) | \
 130                                         ((e & 0x01) << 7)
 131
 132 /* Mode 1 - Battery fuel guage read / write */
 133
 134 #define PSM_BQRW_CACHED         0x80
 135 #define PSM_BQRW_REGMASK        0x1f
 136
 137 /* Mode 2 - Battery control block read / write */
 138
 139 #define PSM_BCB_BATC0           0x00
 140 #define PSM_BCB_BATC1           0x01
 141 #define PSM_BCB_BATC2           0x02
 142 #define PSM_BCB_BATC3           0x03
 143 #define PSM_BCB_BATC4           0x04
 144
 145 #define PSM_BCB_CR              0x01    /* Calibration required */
 146 #define PSM_BCB_BCF             0x02    /* Battery control block failure */
 147 #define PSM_BCB_FGF             0x04    /* Fuel guage failure */
 148 #define PSM_BCB_FULL            0x08    /* Battery is full */
 149 #define PSM_BCB_CHG             0x10    /* Battery pack charging */
 150 #define PSM_BCB_USE             0x20    /* Battery pack in use */
 151 #define PSM_BCB_E               0x40    /* Battery pack enabled */
 152 #define PSM_BCB_IN              0x80    /* Battery pack in use */
 153
 154 /* Mode 4 - Miscellaneous control/status registers */
 155
 156 #define PSM_MISC_HVER   0x00    /* Hardware version number */
 157 #define PSM_MISC_FVER   0x01    /* Firmware version number */
 158 #define PSM_MISC_BLITE  0x10    /* Backlight intensity register */
 159 #define PSM_MISC_IMR    0x20    /* Interrupt mask register */
 160 #define PSM_MISC_UPS    0x21    /* UPS battery pack number */
 161 #define PSM_MISC_FMTA   0x30    /* Battery format registers */
 162 #define PSM_MISC_FMTB   0x31    /* Battery format registers */
 163 #define PSM_MISC_FMTC   0x32    /* Battery format registers */
 164 #define PSM_MISC_FMTD   0x33    /* Battery format registers */
 165 #define PSM_MISC_FAN0   0x40    /* Fan control */
 166 #define PSM_MISC_FAN1   0x41    /* Fan control */
 167 #define PSM_MISC_FAN2   0x42    /* Fan control */
 168 #define PSM_MISC_FAN3   0x43    /* Fan control */
 169 #define PSM_MISC_FAN4   0x44    /* Fan control */
 170 #define PSM_MISC_AD0    0x50    /* Processor internal thermal */
 171 #define PSM_MISC_AD1    0x51    /* Processor vicinity thermal */
 172 #define PSM_MISC_AD2    0x52    /* Processor case thermal */
 173 #define PSM_MISC_AD3    0x53    /* Clamshell ambient  thermal */
 174 #define PSM_MISC_AD4    0x54    /* Reserved */
 175 #define PSM_MISC_AD5    0x55    /* Reserved */
 176 #define PSM_MISC_AD6    0x56    /* Reserved */
 177 #define PSM_MISC_AD7    0x57    /* Discharge bus voltage */
 178 #define PSM_MISC_XMON   0x60    /* External monitor */
 179 #define PSM_MISC_PCYCLE 0x70    /* Power cycle */
 180 #define PSM_MISC_ERROR0 0x80
 181 #define PSM_MISC_ERROR1 0x81
 182 #define PSM_MISC_PEM    0x90
 183 #define PSM_MISC_PEMAD0 0xa0
 184 #define PSM_MISC_PEMAD1 0xa1
 185 #define PSM_MISC_PEMAD2 0xa2
 186 #define PSM_MISC_PEMAD3 0xa3
 187
 188 /* Masks */
 189
 190 #define PSM_FAN_MASK    0x1f    /* 0-31 */
 191
 192 /* Interrupt mask register defenitions */
 193
 194 #define PSM_IMR_MBCC    0x40    /* Battery config change interrupt */
 195 #define PSM_IMR_MTMP    0x20    /* Over temp interrupt */
 196 #define PSM_IMR_MLIDC   0x10    /* Lid close interrupt */
 197 #define PSM_IMR_MLIDO   0x08    /* Lid close interrupt */
 198 #define PSM_IMR_MD      0x04    /* Dock/undock interrupts */
 199 #define PSM_IMR_MPS     0x01    /* Master power switch interrupt */
 200
 201 #define PSM_IMR_ALL     PSM_IMR_MBCC|PSM_IMR_MTMP|PSM_IMR_MLIDO|PSM_IMR_MLIDC \
 202                         |PSM_IMR_MD|PSM_IMR_MPS
 203
 204 /* Battery information */
 205
 206 #define PSM_MAX_BATTERIES       1
 207 #define PSM_VBATT               11100   /* 11.1v nominal battery voltage */
 208
 209 #endif /* PSMREG_H */