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[netbsd-mini2440.git] / sys / arch / sparc64 / dev / psychoreg.h
blob05e4bc85eaeaf53447c92094343f81e456c4008a
1 /* $NetBSD: psychoreg.h,v 1.13 2006/02/25 00:58:35 wiz Exp $ */
2
3 /*
4 * Copyright (c) 1999 Matthew R. Green
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Copyright (c) 1998, 1999 Eduardo E. Horvath
31 * All rights reserved.
32 *
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 * 3. The name of the author may not be used to endorse or promote products
42 * derived from this software without specific prior written permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
55 */
56 #ifndef _SPARC64_DEV_PSYCHOREG_H_
57 #define _SPARC64_DEV_PSYCHOREG_H_
58
59 /*
60 * Sun4u PCI definitions. Here's where we deal w/the machine
61 * dependencies of psycho and the PCI controller on the UltraIIi.
62 *
63 * All PCI registers are bit-swapped, however they are not byte-swapped.
64 * This means that they must be accessed using little-endian access modes,
65 * either map the pages little-endian or use little-endian ASIs.
66 *
67 * PSYCHO implements two PCI buses, A and B.
68 */
69
70 struct psychoreg {
71 struct upareg {
72 uint64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */
73 uint64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */
74 } sys_upa;
75
76 uint64_t psy_csr; /* PSYCHO control/status register */ /* 1fe.0000.0010 */
77 /*
78 * 63 59 55 50 45 4 3 2 1 0
79 * +------+------+------+------+--//---+--------+-------+-----+------+
80 * | IMPL | VERS | MID | IGN | xxx | APCKEN | APERR | IAP | MODE |
81 * +------+------+------+------+--//---+--------+-------+-----+------+
82 *
83 */
84 #define PSYCHO_GCSR_IMPL(csr) ((u_int)(((csr) >> 60) & 0xf))
85 #define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf))
86 #define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f))
87 #define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f))
88 #define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */
89 #define PSYCHO_CSR_APERR 4 /* UPA addr parity error */
90 #define PSYCHO_CSR_IAP 2 /* invert UPA address parity */
91 #define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */
92
93 uint64_t pad0;
94 uint64_t psy_ecccr; /* ECC control register */ /* 1fe.0000.0020 */
95 uint64_t reserved; /* 1fe.0000.0028 */
96 uint64_t psy_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */
97 #define PSYCHO_UE_AFSR_BITS "\177\020" \
98 "b\27BLK\0b\070P_DTE\0b\071S_DTE\0b\072S_DWR\0b\073S_DRD\0b" \
99 "\075P_DWR\0b\076P_DRD\0\0"
100 uint64_t psy_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */
101 uint64_t psy_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */
102 uint64_t psy_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */
103
104 uint64_t pad1[22];
105
106 struct perfmon {
107 uint64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */
108 uint64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */
109 } psy_pm;
110
111 uint64_t pad2[30];
112
113 struct iommureg psy_iommu; /* 1fe.0000.0200,0210 */
114
115 uint64_t pad3[317];
116
117 uint64_t pcia_slot0_int; /* PCI bus a slot 0 irq map reg */ /* 1fe.0000.0c00 */
118 uint64_t pcia_slot1_int; /* PCI bus a slot 1 irq map reg */ /* 1fe.0000.0c08 */
119 uint64_t pcia_slot2_int; /* PCI bus a slot 2 irq map reg (IIi)*/ /* 1fe.0000.0c10 */
120 uint64_t pcia_slot3_int; /* PCI bus a slot 3 irq map reg (IIi)*/ /* 1fe.0000.0c18 */
121 uint64_t pcib_slot0_int; /* PCI bus b slot 0 irq map reg */ /* 1fe.0000.0c20 */
122 uint64_t pcib_slot1_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c28 */
123 uint64_t pcib_slot2_int; /* PCI bus b slot 2 irq map reg */ /* 1fe.0000.0c30 */
124 uint64_t pcib_slot3_int; /* PCI bus b slot 3 irq map reg */ /* 1fe.0000.0c38 */
125
126 uint64_t pad4[120];
127
128 uint64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.1000 */
129 uint64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.1008 */
130 uint64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.1010 */
131 uint64_t audior_int_map; /* audio record interrupt map reg */ /* 1fe.0000.1018 */
132 uint64_t audiop_int_map; /* audio playback interrupt map reg */ /* 1fe.0000.1020 */
133 uint64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.1028 */
134 uint64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.1030 */
135 uint64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.1038 */
136 uint64_t spare_int_map; /* spare interrupt map reg */ /* 1fe.0000.1040 */
137 uint64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.1048 */
138 uint64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.1050 */
139 uint64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.1058 */
140 uint64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.1060 */
141 uint64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.1068 */
142 uint64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.1070 */
143 uint64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.1078 */
144 uint64_t pciaerr_int_map; /* PCI bus a error interrupt map reg */ /* 1fe.0000.1080 */
145 uint64_t pciberr_int_map; /* PCI bus b error interrupt map reg */ /* 1fe.0000.1088 */
146 uint64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.1090 */
147 uint64_t ffb0_int_map; /* FFB0 graphics interrupt map reg */ /* 1fe.0000.1098 */
148 uint64_t ffb1_int_map; /* FFB1 graphics interrupt map reg */ /* 1fe.0000.10a0 */
149
150 uint64_t pad5[107];
151
152 /* Note: clear interrupt 0 registers are not really used */
153 uint64_t pcia0_clr_int[4]; /* PCI a slot 0 clear int regs 0..7 */ /* 1fe.0000.1400-1418 */
154 uint64_t pcia1_clr_int[4]; /* PCI a slot 1 clear int regs 0..7 */ /* 1fe.0000.1420-1438 */
155 uint64_t pcia2_clr_int[4]; /* PCI a slot 2 clear int regs 0..7 */ /* 1fe.0000.1440-1458 */
156 uint64_t pcia3_clr_int[4]; /* PCI a slot 3 clear int regs 0..7 */ /* 1fe.0000.1480-1478 */
157 uint64_t pcib0_clr_int[4]; /* PCI b slot 0 clear int regs 0..7 */ /* 1fe.0000.1480-1498 */
158 uint64_t pcib1_clr_int[4]; /* PCI b slot 1 clear int regs 0..7 */ /* 1fe.0000.14a0-14b8 */
159 uint64_t pcib2_clr_int[4]; /* PCI b slot 2 clear int regs 0..7 */ /* 1fe.0000.14c0-14d8 */
160 uint64_t pcib3_clr_int[4]; /* PCI b slot 3 clear int regs 0..7 */ /* 1fe.0000.14d0-14f8 */
161
162 uint64_t pad6[96];
163
164 uint64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.1800 */
165 uint64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.1808 */
166 uint64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.1810 */
167 uint64_t audior_clr_int; /* audio record clear int reg */ /* 1fe.0000.1818 */
168 uint64_t audiop_clr_int; /* audio playback clear int reg */ /* 1fe.0000.1820 */
169 uint64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.1828 */
170 uint64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.1830 */
171 uint64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.1838 */
172 uint64_t spare_clr_int; /* spare clear int reg */ /* 1fe.0000.1840 */
173 uint64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.1848 */
174 uint64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.1850 */
175 uint64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.1858 */
176 uint64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.1860 */
177 uint64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.1868 */
178 uint64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.1870 */
179 uint64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.1878 */
180 uint64_t pciaerr_clr_int; /* PCI bus a error clear int reg */ /* 1fe.0000.1880 */
181 uint64_t pciberr_clr_int; /* PCI bus b error clear int reg */ /* 1fe.0000.1888 */
182 uint64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.1890 */
183
184 uint64_t pad7[45];
185
186 uint64_t intr_retry_timer; /* interrupt retry timer */ /* 1fe.0000.1a00 */
187
188 uint64_t pad8[63];
189
190 struct timer_counter {
191 uint64_t tc_count; /* timer/counter 0/1 count register */ /* 1fe.0000.1c00,1c10 */
192 uint64_t tc_limit; /* timer/counter 0/1 limit register */ /* 1fe.0000.1c08,1c18 */
193 } tc[2];
194
195 uint64_t pci_dma_write_sync; /* PCI DMA write sync register (IIi) */ /* 1fe.0000.1c20 */
196
197 uint64_t pad9[123];
198
199 struct pci_ctl {
200 uint64_t pci_csr; /* PCI a/b control/status register */ /* 1fe.0000.2000,4000 */
201 uint64_t pad10;
202 uint64_t pci_afsr; /* PCI a/b AFSR register */ /* 1fe.0000.2010,4010 */
203 uint64_t pci_afar; /* PCI a/b AFAR register */ /* 1fe.0000.2018,4018 */
204 uint64_t pci_diag; /* PCI a/b diagnostic register */ /* 1fe.0000.2020,4020 */
205 uint64_t pci_tasr; /* PCI target address space reg (IIi)*/ /* 1fe.0000.2028,4028 */
206
207 uint64_t pad11[250];
208
209 /* This is really the IOMMU's, not the PCI bus's */
210 struct iommu_strbuf pci_strbuf; /* 1fe.0000.2800-210 */
211 #define psy_iommu_strbuf psy_pcictl[0].pci_strbuf
212
213 uint64_t pad12[765];
214 } psy_pcictl[2]; /* For PCI a and b */
215
216 /* NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and 1fe.0000.8000 respectively */
217 uint64_t pad13[2048];
218
219 uint64_t dma_scb_diag0; /* DMA scoreboard diag reg 0 */ /* 1fe.0000.a000 */
220 uint64_t dma_scb_diag1; /* DMA scoreboard diag reg 1 */ /* 1fe.0000.a008 */
221
222 uint64_t pad14[126];
223
224 uint64_t iommu_svadiag; /* IOMMU virtual addr diag reg */ /* 1fe.0000.a400 */
225 uint64_t iommu_tlb_comp_diag; /* IOMMU TLB tag compare diag reg */ /* 1fe.0000.a408 */
226
227 uint64_t pad15[30];
228
229 uint64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.a500-a578 */
230 uint64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.a580-a5f8 */
231 uint64_t tlb_data_diag[16]; /* TLB data RAM diag */ /* 1fe.0000.a600-a678 */
232
233 uint64_t pad16[48];
234
235 uint64_t pci_int_diag; /* PCI int state diag reg */ /* 1fe.0000.a800 */
236 uint64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.a808 */
237
238 uint64_t pad17[254];
239
240 struct strbuf_diag {
241 uint64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.b000-b3f8 */
242 uint64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */
243 uint64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.b800-b878 */
244 uint64_t pad18[16];
245 uint64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.b900-b978 */
246 uint64_t pad19[208];
247 } psy_strbufdiag[2]; /* For PCI a and b */
248
249 /*
250 * Here is the rest of the map, which we're not specifying:
251 *
252 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space
253 * 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header
254 * 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header
255 * 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space
256 * 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space
257 * 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space
258 * 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space
259 *
260 * NB: config and I/O space can use 1-4 byte accesses, not 8 byte
261 * accesses. Memory space can use any sized accesses.
262 *
263 * Note that the SUNW,sabre/SUNW,simba combinations found on the
264 * Ultra5 and Ultra10 machines uses slightly differrent addresses
265 * than the above. This is mostly due to the fact that the APB is
266 * a multi-function PCI device with two PCI bridges, and the U2P is
267 * two separate PCI bridges. It uses the same PCI configuration
268 * space, though the configuration header for each PCI bus is
269 * located differently due to the SUNW,simba PCI busses being
270 * function 0 and function 1 of the APB, whereas the psycho's are
271 * each their own PCI device. The I/O and memory spaces are each
272 * split into 8 equally sized areas (8x2MB blocks for I/O space,
273 * and 8x512MB blocks for memory space). These are allocated in to
274 * either PCI A or PCI B, or neither in the APB's `I/O Address Map
275 * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf)
276 * registers of each simba. We must ensure that both of the
277 * following are correct (the prom should do this for us):
278 *
279 * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0
280 *
281 * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0
282 *
283 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space
284 * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header
285 * 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header
286 * 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided)
287 * 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided)
288 */
289 };
290
291 /* what the bits mean! */
292
293 /* PCI [a|b] control/status register */
294 /* note that the sabre only has one set of PCI control/status registers */
295 #define PCICTL_MRLM 0x0000001000000000LL /* Memory Read Line/Multiple */
296 #define PCICTL_SERR 0x0000000400000000LL /* SERR asserted; W1C */
297 #define PCICTL_ARB_PARK 0x0000000000200000LL /* PCI arbitration parking */
298 #define PCICTL_CPU_PRIO 0x0000000000100000LL /* PCI arbitration parking */
299 #define PCICTL_ARB_PRIO 0x00000000000f0000LL /* PCI arbitration parking */
300 #define PCICTL_ERRINTEN 0x0000000000000100LL /* PCI error interrupt enable */
301 #define PCICTL_RTRYWAIT 0x0000000000000080LL /* PCI error interrupt enable */
302 #define PCICTL_4ENABLE 0x000000000000000fLL /* enable 4 PCI slots */
303 #define PCICTL_6ENABLE 0x000000000000003fLL /* enable 6 PCI slots */
304
305 /*
306 * these are the PROM structures we grovel
307 */
308
309 /*
310 * For the physical addresses split into 3 32 bit values, we deocde
311 * them like the following (IEEE1275 PCI Bus binding 2.0, 2.2.1.1
312 * Numerical Representation):
313 *
314 * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
315 * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
316 * phys.lo cell: llllllll llllllll llllllll llllllll
317 *
318 * where these bits affect the address' properties:
319 * n not-relocatable
320 * p prefetchable
321 * t aliased (non-relocatable IO), below 1MB (memory) or
322 * below 64KB (reloc. IO)
323 * ss address space code:
324 * 00 - configuration space
325 * 01 - I/O space
326 * 10 - 32 bit memory space
327 * 11 - 64 bit memory space
328 * bb..bb 8 bit bus number
329 * ddddd 5 bit device number
330 * fff 3 bit function number
331 * rr..rr 8 bit register number
332 * hh..hh 32 bit unsigned value
333 * ll..ll 32 bit unsigned value
334 * the values of hh..hh and ll..ll are combined to form a larger number.
335 *
336 * For config space, we don't have to do much special. For I/O space,
337 * hh..hh must be zero, and if n == 0 ll..ll is the offset from the
338 * start of I/O space, otherwise ll..ll is the I/O space. For memory
339 * space, hh..hh must be zero for the 32 bit space, and is the high 32
340 * bits in 64 bit space, with ll..ll being the low 32 bits in both cases,
341 * with offset handling being driver via `n == 0' as for I/O space.
342 */
343
344 /* commonly used */
345 #define TAG2BUS(tag) ((tag) >> 16) & 0xff;
346 #define TAG2DEV(tag) ((tag) >> 11) & 0x1f;
347 #define TAG2FN(tag) ((tag) >> 8) & 0x7;
348
349 struct psycho_registers {
350 uint32_t phys_hi;
351 uint32_t phys_mid;
352 uint32_t phys_lo;
353 uint32_t size_hi;
354 uint32_t size_lo;
355 };
356
357 struct psycho_ranges {
358 uint32_t cspace;
359 uint32_t child_hi;
360 uint32_t child_lo;
361 uint32_t phys_hi;
362 uint32_t phys_lo;
363 uint32_t size_hi;
364 uint32_t size_lo;
365 };
366
367 struct psycho_interrupt_map {
368 uint32_t phys_hi;
369 uint32_t phys_mid;
370 uint32_t phys_lo;
371 uint32_t intr;
372 int32_t child_node;
373 uint32_t child_intr;
374 };
375
376 struct psycho_interrupt_map_mask {
377 uint32_t phys_hi;
378 uint32_t phys_mid;
379 uint32_t phys_lo;
380 uint32_t intr;
381 };
382
383 #endif /* _SPARC64_DEV_PSYCHOREG_H_ */
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