sys/arch/sun3/dev/dmareg.h

   1 /*      $NetBSD: dmareg.h,v 1.5 2005/12/11 12:19:20 christos Exp $ */
   2
   3 /*
   4  * Copyright (c) 1994 Peter Galbavy.  All rights reserved.
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Peter Galbavy.
  16  * 4. The name of the author may not be used to endorse or promote products
  17  *    derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #define DMACSRBITS "\020\01INT\02ERR\03DR1\04DR2\05IEN\011WRITE\016ENCNT\017TC\032DMAON"
  32
  33 #define DMAREG_SIZE             0x10
  34
  35 #define DMA_REG_CSR             0x00
  36 #define DMA_REG_ADDR            0x04
  37 #define DMA_REG_BCNT            0x08
  38 #define DMA_REG_TEST            0x0c
  39
  40 struct dma_regs {
  41         uint32_t        csr;            /* DMA CSR */
  42         /* bits common to all revs. */
  43 #define  D_INT_PEND     0x00000001      /* interrupt pending */
  44 #define  D_ERR_PEND     0x00000002      /* error pending */
  45 #define  D_PACKCNT      0x0000000c      /* byte pack count */
  46 #define  D_INT_EN       0x00000010      /* interrupt enable */
  47 #define  D_FLUSH        0x00000020      /* invalidate fifo */
  48 #define  D_DRAIN        0x00000040      /* drain fifo */
  49 #define  D_RESET        0x00000080      /* reset scsi */
  50 #define  D_WRITE        0x00000100      /* device -> mem */
  51 #define  D_EN_DMA       0x00000200      /* enable DMA requests */
  52 #define  D_R_PEND       0x00000400      /* REV1,ESC: request pending */
  53 #define  D_BYTEADR      0x00001800      /* REV1: next byte address */
  54 #define  D_EN_CNT       0x00002000      /* REV1: enable byte counter */
  55 #define  D_TC           0x00004000      /* REV1,2: terminal count */
  56
  57 #define  D_BURST_SIZE   0x000c0000      /* read/write burst size */
  58 #define   D_BURST_16    0x00000000      /*   16-byte bursts */
  59 #define   D_BURST_32    0x00040000      /*   32-byte bursts */
  60 #define   D_BURST_0     0x00080000      /*   no bursts (SCSI-only) */
  61
  62 #define  D_TWO_CYCLE    0x00200000      /* REV3: 2 clocks per transfer */
  63 #define  D_FASTER       0x00400000      /* 3 clocks per transfer */
  64 #define  D_TCI_DIS      0x00800000      /* disable intr on D_TC */
  65
  66 #define  D_EN_NEXT      0x01000000      /* enable auto next address */
  67 #define  D_DMA_ON       0x02000000      /* enable dma from scsi */
  68 #define  D_A_LOADED     0x04000000      /* address loaded */
  69 #define  D_NA_LOADED    0x08000000      /* next address loaded */
  70
  71 #define  D_DEV_ID       0xf0000000      /* device ID */
  72 #define   DMAREV_0      0x00000000      /* Sunray DMA */
  73 #define   DMAREV_ESC    0x40000000      /*  DMA ESC array */
  74 #define   DMAREV_1      0x80000000      /* 'DMA' */
  75 #define   DMAREV_PLUS   0x90000000      /* 'DMA+' */
  76 #define   DMAREV_2      0xa0000000      /* 'DMA2' */
  77
  78         uint32_t        addr;
  79 #define DMA_D_ADDR              0x01            /* DMA ADDR (in longs) */
  80
  81         uint32_t        bcnt;           /* DMA COUNT (in longs) */
  82 #define  D_BCNT_MASK            0x00ffffff      /* only 24 bits */
  83
  84         uint32_t        test;           /* DMA TEST (in longs) */
  85 #define en_testcsr      addr                    /* enet registers overlap */
  86 #define en_cachev       bcnt
  87 #define en_bar          test
  88 };