sys/arch/sun3/dev/dmavar.h

   1 /*      $NetBSD: dmavar.h,v 1.9 2007/03/04 14:00:24 tsutsui Exp $ */
   2
   3 /*
   4  * Copyright (c) 1994 Peter Galbavy.  All rights reserved.
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Peter Galbavy.
  16  * 4. The name of the author may not be used to endorse or promote products
  17  *    derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 struct dma_softc {
  32         device_t sc_dev;                        /* us as a device */
  33         bus_space_tag_t sc_bst;                 /* bus space tag */
  34         bus_dma_tag_t sc_dmatag;                /* bus dma tag */
  35
  36         bus_space_handle_t sc_bsh;              /* bus space handle */
  37         void *sc_client;                        /* my client */
  38
  39         int     sc_active;                      /* DMA active ? */
  40         bus_dmamap_t sc_dmamap;                 /* bus dma map */
  41         u_int   sc_rev;                         /* revision */
  42         int     sc_burst;                       /* DVMA burst size in effect */
  43         size_t  sc_dmasize;
  44         uint8_t **sc_dmaaddr;
  45         size_t  *sc_dmalen;
  46 #if 0
  47         void (*reset)(struct dma_softc *);      /* reset routine */
  48         int (*intr)(struct dma_softc *);        /* interrupt ! */
  49         int (*setup)(struct dma_softc *, uint8_t **, size_t *, int, size_t *);
  50 #endif
  51 };
  52
  53 #define DMA_GCSR(sc)            \
  54         bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, DMA_REG_CSR)
  55 #define DMA_SCSR(sc, csr)       \
  56         bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, DMA_REG_CSR, (csr))
  57
  58 /*
  59  * DMA engine interface functions.
  60  */
  61 #if 0
  62 #define DMA_RESET(sc)                   (((sc)->reset)(sc))
  63 #define DMA_INTR(sc)                    (((sc)->intr)(sc))
  64 #define DMA_SETUP(sc, a, l, d, s)       (((sc)->setup)(sc, a, l, d, s))
  65 #endif
  66
  67 #define DMA_ISACTIVE(sc)                ((sc)->sc_active)
  68
  69 #define DMA_ENINTR(sc) do {                     \
  70         uint32_t _csr = DMA_GCSR(sc);           \
  71         _csr |= D_INT_EN;                       \
  72         DMA_SCSR(sc, _csr);                     \
  73 } while (/* CONSTCOND */0)
  74
  75 #define DMA_ISINTR(sc)  (DMA_GCSR(sc) & (D_INT_PEND|D_ERR_PEND))
  76
  77 #define DMA_GO(sc) do {                         \
  78         uint32_t _csr = DMA_GCSR(sc);           \
  79         _csr |= D_EN_DMA;                       \
  80         DMA_SCSR(sc, _csr);                     \
  81         sc->sc_active = 1;                      \
  82 } while (/* CONSTCOND */0)
  83
  84 #define DMA_STOP(sc) do {                       \
  85         uint32_t _csr = DMA_GCSR(sc);           \
  86         _csr &= ~D_EN_DMA;                      \
  87         DMA_SCSR(sc, _csr);                     \
  88         sc->sc_active = 0;                      \
  89 } while (/* CONSTCOND */0)
  90
  91 struct dma_softc *espdmafind(int);
  92 int espdmaintr(struct dma_softc *);
  93
  94 void dma_reset(struct dma_softc *);
  95 int  dma_setup(struct dma_softc *, uint8_t **, size_t *, int, size_t *);
  96