sys/arch/vax/if/if_zereg.h

   1 /*      $NetBSD: if_zereg.h,v 1.1.48.3 2004/09/21 13:23:42 skrll Exp $  */
   2 /*
   3  * Copyright (c) 1988 Regents of the University of California.
   4  * All rights reserved.
   5  *
   6  * This code is derived from software contributed to Berkeley by
   7  * Digital Equipment Corp.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  */
  34
  35
  36 /* Driver for SGEC (second generation Ethernet controller) chip, type DC-541,
  37    found on the KA670 (and prob ably other) CPU.
  38
  39    17 May 1998...Jay Maynard, jmaynard@phoenix.net
  40 */
  41
  42 /* SGEC CSRs */
  43 struct zedevice {
  44         u_long ze_nicsr0;       /* vector address, IPL, sync mode */
  45         u_long ze_nicsr1;       /* TX poll demand */
  46         u_long ze_nicsr2;       /* RX poll demand */
  47         struct ze_rdes *ze_nicsr3;      /* RX descriptor list address */
  48         struct ze_tdes *ze_nicsr4;      /* TX descriptor list address */
  49         u_long ze_nicsr5;       /* SGEC status */
  50         u_long ze_nicsr6;       /* SGEC command/mode */
  51         u_long ze_nicsr7;       /* system page table base address */
  52         u_long ze_nivcsr8;      /* reserved virtual CSR */
  53         u_long ze_nivcsr9;      /* watchdog timers (virtual) */
  54         u_long ze_nivcsr10;     /* revision, missed frame count (v) */
  55         u_long ze_nivcsr11;     /* boot message verification (low) (v) */
  56         u_long ze_nivcsr12;     /* boot message verification (high) (v) */
  57         u_long ze_nivcsr13;     /* boot message processor (v) */
  58         u_long ze_nivcsr14;     /* diagnostic breakpoint (v) */
  59         u_long ze_nicsr15;      /* monitor command */
  60 };
  61
  62 /* SGEC bit definitions */
  63 /* NICSR0: */
  64 #define ZE_NICSR0_IPL 0xc0000000        /* interrupt priority level: */
  65 #define ZE_NICSR0_IPL14 0x00000000      /* 0x14 */
  66 #define ZE_NICSR0_IPL15 0x40000000      /* 0x15 */
  67 #define ZE_NICSR0_IPL16 0x80000000      /* 0x16 */
  68 #define ZE_NICSR0_IPL17 0xc0000000      /* 0x17 */
  69 #define ZE_NICSR0_SA 0x20000000         /* sync(1)/async mode */
  70 #define ZE_NICSR0_MBO 0x1fff0003        /* must be set to one on write */
  71 #define ZE_NICSR0_IV_MASK 0x0000fffc    /* bits for the interrupt vector */
  72
  73 /* NICSR1: */
  74 #define ZE_NICSR1_TXPD 0xffffffff       /* transmit polling demand */
  75
  76 /* NICSR2: */
  77 #define ZE_NICSR2_RXPD 0xffffffff       /* receive polling demand */
  78
  79 /* NICSR3 and NICSR4 are pure addresses */
  80 /* NICSR5: */
  81 #define ZE_NICSR5_ID 0x80000000         /* init done */
  82 #define ZE_NICSR5_SF 0x40000000         /* self-test failed */
  83 #define ZE_NICSR5_SS 0x3c000000         /* self-test status field */
  84 #define ZE_NICSR5_TS 0x03000000         /* transmission state: */
  85 #define ZE_NICSR5_TS_STOP 0x00000000    /* stopped */
  86 #define ZE_NICSR5_TS_RUN 0x01000000     /* running */
  87 #define ZE_NICSR5_TS_SUSP 0x02000000    /* suspended */
  88 #define ZE_NICSR5_RS 0x00c00000         /* reception state: */
  89 #define ZE_NICSR5_RS_STOP 0x00000000    /* stopped */
  90 #define ZE_NICSR5_RS_RUN 0x00400000     /* running */
  91 #define ZE_NICSR5_RS_SUSP 0x00800000    /* suspended */
  92 #define ZE_NICSR5_OM 0x00060000         /* operating mode: */
  93 #define ZE_NICSR5_OM_NORM 0x00000000    /* normal */
  94 #define ZE_NICSR5_OM_ILBK 0x00020000    /* internal loopback */
  95 #define ZE_NICSR5_OM_ELBK 0x00040000    /* external loopback */
  96 #define ZE_NICSR5_OM_DIAG 0x00060000    /* reserved for diags */
  97 #define ZE_NICSR5_DN 0x00010000         /* virtual CSR access done */
  98 #define ZE_NICSR5_MBO 0x0038ff00        /* must be one */
  99 #define ZE_NICSR5_BO 0x00000080         /* boot message received */
 100 #define ZE_NICSR5_TW 0x00000040         /* transmit watchdog timeout */
 101 #define ZE_NICSR5_RW 0x00000020         /* receive watchdog timeout */
 102 #define ZE_NICSR5_ME 0x00000010         /* memory error */
 103 #define ZE_NICSR5_RU 0x00000008         /* receive buffer unavailable */
 104 #define ZE_NICSR5_RI 0x00000004         /* receiver interrupt */
 105 #define ZE_NICSR5_TI 0x00000002         /* transmitter interrupt */
 106 #define ZE_NICSR5_IS 0x00000001         /* interrupt summary */
 107 /* whew! */
 108
 109 /* NICSR6: */
 110 #define ZE_NICSR6_RE 0x80000000         /* reset */
 111 #define ZE_NICSR6_IE 0x40000000         /* interrupt enable */
 112 #define ZE_NICSR6_MBO 0x01e7f000        /* must be one */
 113 #define ZE_NICSR6_BL 0x1e000000         /* burst limit mask */
 114 #define ZE_NICSR6_BL_8 0x10000000       /* 8 longwords */
 115 #define ZE_NICSR6_BL_4 0x08000000       /* 4 longwords */
 116 #define ZE_NICSR6_BL_2 0x04000000       /* 2 longwords */
 117 #define ZE_NICSR6_BL_1 0x02000000       /* 1 longword */
 118 #define ZE_NICSR6_BE 0x00100000         /* boot message enable */
 119 #define ZE_NICSR6_SE 0x00080000         /* single cycle enable */
 120 #define ZE_NICSR6_ST 0x00000800         /* start(1)/stop(0) transmission */
 121 #define ZE_NICSR6_SR 0x00000400         /* start(1)/stop(0) reception */
 122 #define ZE_NICSR6_OM 0x00000300         /* operating mode: */
 123 #define ZE_NICSR6_OM_NORM 0x00000000    /* normal */
 124 #define ZE_NICSR6_OM_ILBK 0x00000100    /* internal loopback */
 125 #define ZE_NICSR6_OM_ELBK 0x00000200    /* external loopback */
 126 #define ZE_NICSR6_OM_DIAG 0x00000300    /* reserved for diags */
 127 #define ZE_NICSR6_DC 0x00000080         /* disable data chaining */
 128 #define ZE_NICSR6_FC 0x00000040         /* force collision mode */
 129 #define ZE_NICSR6_PB 0x00000008         /* pass bad frames */
 130 #define ZE_NICSR6_AF 0x00000006         /* address filtering mode: */
 131 #define ZE_NICSR6_AF_NORM 0x00000000    /* normal filtering */
 132 #define ZE_NICSR6_AF_PROM 0x00000002    /* promiscuous mode */
 133 #define ZE_NICSR6_AF_ALLM 0x00000004    /* all multicasts */
 134
 135 /* NICSR7 is an address, NICSR8 is reserved */
 136 /* NICSR9: */
 137 #define ZE_VNICSR9_RT 0xffff0000        /* receiver timeout, *1.6 us */
 138 #define ZE_VNICSR9_TT 0x0000ffff        /* transmitter timeout */
 139
 140 /* NICSR10: */
 141 #define ZE_VNICSR10_RN 0x001f0000       /* SGEC version */
 142 #define ZE_VNICSR10_MFC 0x0000ffff      /* missed frame counter */
 143
 144 /* if you want to know what's in NICSRs 11-15, define them yourself! */
 145
 146 /* Descriptors: */
 147 /* Receive descriptor */
 148 struct ze_rdes {
 149         u_short ze_rdes0;               /* descriptor word 0 flags */
 150         u_short ze_framelen;            /* received frame length */
 151         u_char ze_rsvd1[3];             /* unused bytes */
 152         u_char ze_rdes1;                /* descriptor word 1 flags */
 153         short ze_pageoffset;            /* offset of buffer in page */
 154         short ze_bufsize;               /* length of data buffer */
 155         u_char *ze_bufaddr;             /* address of data buffer */
 156 };
 157
 158 /* Receive descriptor bits */
 159 #define ZE_FRAMELEN_OW 0x8000           /* SGEC owns this descriptor */
 160 #define ZE_RDES0_ES 0x8000              /* an error has occurred */
 161 #define ZE_RDES0_LE 0x4000              /* length error */
 162 #define ZE_RDES0_DT 0x3000              /* data type: */
 163 #define ZE_RDES0_DT_NORM 0x0000         /* normal frame */
 164 #define ZE_RDES0_DT_ILBK 0x1000         /* internally looped back frame */
 165 #define ZE_RDES0_DT_ELBK 0x2000         /* externally looped back frame */
 166 #define ZE_RDES0_RF 0x0800              /* runt frame */
 167 #define ZE_RDES0_BO 0x0400              /* buffer overflow */
 168 #define ZE_RDES0_FS 0x0200              /* first segment */
 169 #define ZE_RDES0_LS 0x0100              /* last segment */
 170 #define ZE_RDES0_TL 0x0080              /* frame too long */
 171 #define ZE_RDES0_CS 0x0040              /* collision seen */
 172 #define ZE_RDES0_FT 0x0020              /* Ethernet frame type */
 173 #define ZE_RDES0_TN 0x0008              /* address translation not valid */
 174 #define ZE_RDES0_DB 0x0004              /* dribbling bits seen */
 175 #define ZE_RDES0_CE 0x0002              /* CRC error */
 176 #define ZE_RDES0_OF 0x0001              /* internal FIFO overflow */
 177 #define ZE_RDES1_CA 0x80                /* chain address */
 178 #define ZE_RDES1_VA 0x40                /* virtual address */
 179 #define ZE_RDES1_VT 0x20                /* virtual(1)/phys PTE address */
 180
 181 /* Transmit descriptor */
 182 struct ze_tdes {
 183         u_short ze_tdes0;               /* descriptor word 0 flags */
 184         u_short ze_tdr;                 /* TDR count of cable fault */
 185         u_char ze_rsvd1[2];             /* unused bytes */
 186         u_short ze_tdes1;               /* descriptor word 1 flags */
 187         short ze_pageoffset;            /* offset of buffer in page */
 188         short ze_bufsize;               /* length of data buffer */
 189         u_char *ze_bufaddr;             /* address of data buffer */
 190 };
 191
 192 /* Receive descriptor bits */
 193 #define ZE_TDR_OW 0x8000                /* SGEC owns this descriptor */
 194 #define ZE_TDES0_ES 0x8000              /* an error has occurred */
 195 #define ZE_TDES0_TO 0x4000              /* transmit watchdog timeout */
 196 #define ZE_TDES0_LE 0x1000              /* length error */
 197 #define ZE_TDES0_LO 0x0800              /* loss of carrier */
 198 #define ZE_TDES0_NC 0x0400              /* no carrier */
 199 #define ZE_TDES0_LC 0x0200              /* late collision */
 200 #define ZE_TDES0_EC 0x0100              /* excessive collisions */
 201 #define ZE_TDES0_HF 0x0080              /* heartbeat fail */
 202 #define ZE_TDES0_CC 0x0078              /* collision count mask */
 203 #define ZE_TDES0_TN 0x0004              /* address translation invalid */
 204 #define ZE_TDES0_UF 0x0002              /* underflow */
 205 #define ZE_TDES0_DE 0x0001              /* transmission deferred */
 206 #define ZE_TDES1_CA 0x8000              /* chain address */
 207 #define ZE_TDES1_VA 0x4000              /* virtual address */
 208 #define ZE_TDES1_DT 0x3000              /* data type: */
 209 #define ZE_TDES1_DT_NORM 0x0000         /* normal transmit frame */
 210 #define ZE_TDES1_DT_SETUP 0x2000        /* setup frame */
 211 #define ZE_TDES1_DT_DIAG 0x3000         /* diagnostic frame */
 212 #define ZE_TDES1_AC 0x0800              /* CRC disable */
 213 #define ZE_TDES1_FS 0x0400              /* first segment */
 214 #define ZE_TDES1_LS 0x0200              /* last segment */
 215 #define ZE_TDES1_IC 0x0100              /* interrupt on completion */
 216 #define ZE_TDES1_VT 0x0080              /* virtual(1)/phys PTE address */
 217