sys/arch/vax/include/ka410.h

   1 /*      $NetBSD: ka410.h,v 1.4 1998/10/06 04:04:31 matt Exp $ */
   2 /*
   3  * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
   4  * All rights reserved.
   5  *
   6  * This code is derived from software contributed to Ludd by Bertram Barth.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed at Ludd, University of
  19  *      Lule}, Sweden and its contributors.
  20  * 4. The name of the author may not be used to endorse or promote products
  21  *    derived from this software without specific prior written permission
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #ifndef _VAX_KA410_H_
  36 #define _VAX_KA410_H_
  37
  38 /*
  39  * Definition for  I/O addresses of
  40  *
  41  *      MicroVAX 2000   (TeamMate)
  42  *      VAXstation 2000 (VAXstar)
  43  */
  44
  45 #define KA410_SIDEX     0x20040004      /* SID extension register */
  46
  47 #define KA410_CFGTST    0x20020000      /* Configuration and Test register */
  48 #define KA410_IORESET   0x20020000      /* I/O Reset register */
  49
  50 #define KA410_ROM_BASE  0x20040000      /* System module ROM */
  51 #define KA410_ROM_END   0x2007FFFF
  52 #define KA410_ROM_SIZE     0x40000
  53
  54 #define KA410_IVN_BASE  0x20040020      /* Interrupt Vector Numbers */
  55 #define KA410_IVN_END   0x2004003F
  56 #define KA410_IVN_SIZE        0x20
  57
  58 #define KA410_HLTCOD    0x20080000      /* Halt Code Register */
  59 #define KA410_MSER      0x20080004      /* Memory System Error register */
  60 #define KA410_MEAR      0x20080008      /* Memory Error Address register */
  61 #define KA410_INTMSK    0x2008000C      /* Interrupt Mask register */
  62 #define KA410_VDCORG    0x2008000D      /* Video Controller Origin Register */
  63 #define KA410_VDCSEL    0x2008000E      /* Video Controller Select Register */
  64 #define KA410_INTREQ    0x2008000F      /* Interrupt Request register */
  65 #define KA410_INTCLR    0x2008000F      /* Interrupt Request clear register */
  66
  67 /*
  68  * Other fixed addresses which should be mapped
  69  */
  70 #define KA410_CPU_BASE  ((struct ka410_cpu *)0x20080000)
  71 #define KA410_CPU_END   0x200800FF
  72 #define KA410_CPU_SIZE       0x100
  73 #define KA410_NWA_BASE  0x20090000      /* Network Address ROM */
  74 #define KA410_NWA_END   0x2009007F
  75 #define KA410_NWA_SIZE        0x80
  76 #define KA410_SER_BASE  0x200A0000      /* Serial line controller */
  77 #define KA410_SER_END   0x200A000F
  78 #define KA410_SER_SIZE        0x10
  79 #define KA410_WAT_BASE  ((struct ka410_clock *)0x200B0000)/* TOY clock */
  80 #define KA410_WAT_END   0x200B00FF
  81 #define KA410_WAT_SIZE       0x100
  82 #define KA410_DKC_BASE  0x200C0000      /* Disk Controller Ports */
  83 #define KA410_DKC_END   0x200C0007
  84 #define KA410_DKC_SIZE        0x08
  85 #define KA410_SCS_BASE  0x200C0080      /* Tape (SCSI) Controller Chip */
  86 #define KA410_SCS_END   0x200C009F
  87 #define KA410_SCS_SIZE        0x20
  88 #define KA410_DMA_BASE  0x200D0000      /* Disk Data buffer RAM */
  89 #define KA410_DMA_END   0x200D3FFF
  90 #define KA410_DMA_SIZE      0x4000
  91 #define KA410_LAN_BASE  0x200E0000      /* LANCE chip registers */
  92 #define KA410_LAN_END   0x200E0007
  93 #define KA410_LAN_SIZE        0x08
  94 #define KA410_CUR_BASE  0x200F0000      /* Monochrome video cursor chip */
  95 #define KA410_CUR_END   0x200F0007
  96 #define KA410_CUR_SIZE        0x08
  97
  98 #define KA410_SCS_DADR  0x200C00A0      /* Tape(SCSI) DMA address register */
  99 #define KA410_SCS_DCNT  0x200C00C0      /* Tape(SCSI) DMA byte count reg. */
 100 #define KA410_SCS_DDIR  0x200C00C4      /* Tape(SCSI) DMA transfer direction */
 101
 102 #define KA410_CUR_CMD   0x200F0000      /* Cursor Command Register */
 103 #define KA410_CUR_XPOS  0x200F0004      /* Cursor X position */
 104 #define KA410_CUR_YPOS  0x200F0008      /* Cursor Y position */
 105
 106 #define KA410_CUR_XMIN1 0x200F000C      /* Region 1 left edge */
 107 #define KA410_CUR_XMAX1 0x200F0010      /* Region 1 right edge */
 108 #define KA410_CUR_YMIN1 0x200F0014      /* Region 1 top edge */
 109 #define KA410_CUR_YMAX1 0x200F0018      /* Region 1 bottom edge */
 110
 111 #define KA410_CUR_XMIN2 0x200F002C      /* Region 2 left edge */
 112 #define KA410_CUR_XMAX2 0x200F0030      /* Region 2 right edge */
 113 #define KA410_CUR_YMIN2 0x200F0034      /* Region 2 top edge */
 114 #define KA410_CUR_YMAX2 0x200F0038      /* Region 2 bottom edge */
 115
 116 /*
 117  * Definitions for the Configuration and Test Register
 118  */
 119 #define KA410_CFG_MULTU         0x80    /* MicroVAX or VAXstation */
 120 #define KA410_CFG_NETOPT        0x40    /* Network option present */
 121 #define KA410_CFG_L3CON         0x20    /* Console on line #3 of dc */
 122 #define KA410_CFG_CURTEST       0x10    /* Cursor Test (monochrom) */
 123 #define KA410_CFG_VIDOPT        0x08    /* Video option present */
 124 #define KA410_CFG_MEMSZ         0x07    /* Memory option type/size */
 125
 126 #define KA410_CFG_0MB           0x00    /* No additional Memory board */
 127 #define KA410_CFG_1MB           0x01
 128 #define KA410_CFG_2MB           0x02
 129 #define KA410_CFG_4MB           0x03
 130 #define KA410_CFG_6MB           0x04
 131 #define KA410_CFG_8MB           0x05
 132 #define KA410_CFG_12MB          0x06
 133 #define KA410_CFG_14MB          0x07
 134
 135
 136 /*
 137  * interrupt request-, clear-, and mask register
 138  */
 139 extern volatile unsigned char *ka410_intreq;
 140 extern volatile unsigned char *ka410_intclr;
 141 extern volatile unsigned char *ka410_intmsk;
 142
 143 #define INTR_SR (1<<7)  /* Serial line receiver or silo full */
 144 #define INTR_ST (1<<6)  /* Serial line transmitter done */
 145 #define INTR_NP (1<<5)  /* Network controller primary */
 146 #define INTR_NS (1<<4)  /* Network controller secondary */
 147 #define INTR_VF (1<<3)  /* Video end of frame */
 148 #define INTR_VS (1<<2)  /* Video secondary */
 149 #define INTR_SC (1<<1)  /* SCSI controller */
 150 #define INTR_DC (1<<0)  /* Disk controller */
 151
 152 /*
 153  * Clock-Chip data in NVRAM
 154  */
 155 #define KA410_CPMBX     0x200B0038      /* Console Mailbox (1 byte) */
 156 #define KA410_CPFLG     0x200B003C      /* Console Program Flags (1 byte) */
 157 #define KA410_LK201_ID  0x200B0040      /* Keyboard Variation (1 byte) */
 158 #define KA410_CONS_ID   0x200B0044      /* Console Device Type (1 byte) */
 159 #define KA410_SCR       0x200B0048      /* Console Scratch RAM */
 160 #define KA410_TEMP      0x200B0058      /* Used by System Firmware */
 161 #define KA410_BAT_CHK   0x200B0088      /* Battery Check Data */
 162 #define KA410_BOOTDEV   0x200B0098      /* Default Boot Device (4 bytes) */
 163 #define KA410_BOOTFLG   0x200B00A8      /* Default Boot Flags (4 bytes) */
 164 #define KA410_SCRLEN    0x200B00B8      /* Number of pages of SCR (1 byte) */
 165 #define KA410_SCSIPORT  0x200B00BC      /* Tape Controller Port Data */
 166 #define KA410_RESERVED  0x200B00C0      /* Reserved (16 bytes) */
 167
 168
 169 struct ka410_cpu {
 170         u_long  ka410_hltcod;
 171         u_long  ka410_mser;
 172         u_long  ka410_cear;
 173         u_long  ka410_intmsk;
 174 };
 175
 176 /*
 177  * KA410 uses bits 2-9 of longwords to store single bytes in NVRAM,
 178  * thus we declare the clock as an struct of bit-fields, so that the
 179  * generic clock-routines work for KA410...
 180  */
 181 struct ka410_clock {
 182         u_long  :2;     u_long  sec     :8;     u_long  :22;
 183         u_long  :2;     u_long  secalrm :8;     u_long  :22;
 184         u_long  :2;     u_long  min     :8;     u_long  :22;
 185         u_long  :2;     u_long  minalrm :8;     u_long  :22;
 186         u_long  :2;     u_long  hr      :8;     u_long  :22;
 187         u_long  :2;     u_long  hralrm  :8;     u_long  :22;
 188         u_long  :2;     u_long  dayofwk :8;     u_long  :22;
 189         u_long  :2;     u_long  day     :8;     u_long  :22;
 190         u_long  :2;     u_long  mon     :8;     u_long  :22;
 191         u_long  :2;     u_long  yr      :8;     u_long  :22;
 192         u_long  :2;     u_long  csr0    :8;     u_long  :22;
 193         u_long  :2;     u_long  csr1    :8;     u_long  :22;
 194         u_long  :2;     u_long  csr2    :8;     u_long  :22;
 195         u_long  :2;     u_long  csr3    :8;     u_long  :22;
 196         u_long  :2;     u_long  cpmbx   :8;     u_long  :22;
 197 };
 198
 199 #endif /* _VAX_KA410_H_ */