sys/arch/vax/include/mtpr.h

   1 /*      $NetBSD: mtpr.h,v 1.21 2009/05/13 03:40:13 mhitch Exp $     */
   2
   3 /*
   4  * Copyright (c) 1994 Ludd, University of Lule}, Sweden.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *     This product includes software developed at Ludd, University of Lule}.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33  /* All bugs are subject to removal without further notice */
  34
  35 #ifndef _VAX_MTPR_H_
  36 #define _VAX_MTPR_H_
  37
  38 /******************************************************************************
  39
  40   Processor register numbers in the VAX         /IC
  41
  42 ******************************************************************************/
  43
  44
  45 #define PR_KSP     0 /* Kernel Stack Pointer */
  46 #define PR_ESP     1 /* Executive Stack Pointer */
  47 #define PR_SSP     2 /* Supervisor Stack Pointer */
  48 #define PR_USP     3 /* User Stack Pointer */
  49 #define PR_ISP     4 /* Interrupt Stack Pointer */
  50
  51 #define PR_P0BR    8 /* P0 Base Register */
  52 #define PR_P0LR    9 /* P0 Length Register */
  53 #define PR_P1BR   10 /* P1 Base Register */
  54 #define PR_P1LR   11 /* P1 Length Register */
  55 #define PR_SBR    12 /* System Base Register */
  56 #define PR_SLR    13 /* System Limit Register */
  57 #define PR_PCBB   16 /* Process Control Block Base */
  58 #define PR_SCBB   17 /* System Control Block Base */
  59 #define PR_IPL    18 /* Interrupt Priority Level */
  60 #define PR_ASTLVL 19 /* AST Level */
  61 #define PR_SIRR   20 /* Software Interrupt Request */
  62 #define PR_SISR   21 /* Software Interrupt Summary */
  63 #define PR_IPIR   22 /* KA820 Interprocessor register */
  64 #define PR_MCSR   23 /* Machine Check Status Register 11/750 */
  65 #define PR_ICCS   24 /* Interval Clock Control */
  66 #define PR_NICR   25 /* Next Interval Count */
  67 #define PR_ICR    26 /* Interval Count */
  68 #define PR_TODR   27 /* Time Of Year (optional) */
  69 #define PR_CSRS   28 /* Console Storage R/S */
  70 #define PR_CSRD   29 /* Console Storage R/D */
  71 #define PR_CSTS   30 /* Console Storage T/S */
  72 #define PR_CSTD   31 /* Console Storage T/D */
  73 #define PR_RXCS   32 /* Console Receiver C/S */
  74 #define PR_RXDB   33 /* Console Receiver D/B */
  75 #define PR_TXCS   34 /* Console Transmit C/S */
  76 #define PR_TXDB   35 /* Console Transmit D/B */
  77 #define PR_TBDR   36 /* Translation Buffer Group Disable Register 11/750 */
  78 #define PR_CADR   37 /* Cache Disable Register 11/750 */
  79 #define PR_MCESR  38 /* Machiune Check Error Summary Register 11/750 */
  80 #define PR_CAER   39 /* Cache Error Register 11/750 */
  81 #define PR_ACCS   40 /* Accelerator control register */
  82 #define PR_SAVISP 41 /* Console Saved ISP */
  83 #define PR_SAVPC  42 /* Console Saved PC */
  84 #define PR_SAVPSL 43 /* Console Saved PSL */
  85 #define PR_WCSA   44 /* WCS Address */
  86 #define PR_WCSB   45 /* WCS Data */
  87 #define PR_SBIFS  48 /* SBI Fault/Status */
  88 #define PR_SBIS   49 /* SBI Silo */
  89 #define PR_SBISC  50 /* SBI Silo Comparator */
  90 #define PR_SBIMT  51 /* SBI Silo Maintenance */
  91 #define PR_SBIER  52 /* SBI Error Register */
  92 #define PR_SBITA  53 /* SBI Timeout Address Register */
  93 #define PR_SBIQC  54 /* SBI Quadword Clear */
  94 #define PR_IUR    55 /* Initialize Unibus Register 11/750 */
  95 #define PR_MAPEN  56 /* Memory Management Enable */
  96 #define PR_TBIA   57 /* Trans. Buf. Invalidate All */
  97 #define PR_TBIS   58 /* Trans. Buf. Invalidate Single */
  98 #define PR_TBDATA 59 /* Translation Buffer Data */
  99 #define PR_MBRK   60 /* Microprogram Break */
 100 #define PR_PMR    61 /* Performance Monnitor Enable */
 101 #define PR_SID    62 /* System ID Register */
 102 #define PR_TBCHK  63 /* Translation Buffer Check */
 103
 104 #define PR_PAMACC 64 /* Physical Address Memory Map Access (KA86) */
 105 #define PR_PAMLOC 65 /* Physical Address Memory Map Location (KA86) */
 106 #define PR_CSWP   66 /* Cache Sweep (KA86) */
 107 #define PR_MDECC  67 /* MBOX Data Ecc Register (KA86) */
 108 #define PR_MENA   68 /* MBOX Error Enable Register (KA86) */
 109 #define PR_MDCTL  69 /* MBOX Data Control Register (KA86) */
 110 #define PR_MCCTL  70 /* MBOX Mcc Control Register (KA86) */
 111 #define PR_MERG   71 /* MBOX Error Generator Register (KA86) */
 112 #define PR_CRBT   72 /* Console Reboot (KA86) */
 113 #define PR_DFI    73 /* Diagnostic Fault Insertion Register (KA86) */
 114 #define PR_EHSR   74 /* Error Handling Status Register (KA86) */
 115 #define PR_STXCS  76 /* Console Storage C/S (KA86) */
 116 #define PR_STXDB  77 /* Console Storage D/B (KA86) */
 117 #define PR_ESPA   78 /* EBOX Scratchpad Address (KA86) */
 118 #define PR_ESPD   79 /* EBOX Scratchpad Data (KA86) */
 119
 120 #define PR_RXCS1  80 /* Serial-Line Unit 1 Receive CSR (KA820) */
 121 #define PR_RXDB1  81 /* Serial-Line Unit 1 Receive Data Buffer (KA820) */
 122 #define PR_TXCS1  82 /* Serial-Line Unit 1 Transmit CSR (KA820) */
 123 #define PR_TXDB1  83 /* Serial-Line Unit 1 Transmit Data Buffer (KA820) */
 124 #define PR_RXCS2  84 /* Serial-Line Unit 2 Receive CSR (KA820) */
 125 #define PR_RXDB2  85 /* Serial-Line Unit 2 Receive Data Buffer (KA820) */
 126 #define PR_TXCS2  86 /* Serial-Line Unit 2 Transmit CSR (KA820) */
 127 #define PR_TXDB2  87 /* Serial-Line Unit 2 Transmit Data Buffer (KA820) */
 128 #define PR_RXCS3  88 /* Serial-Line Unit 3 Receive CSR (KA820) */
 129 #define PR_RXDB3  89 /* Serial-Line Unit 3 Receive Data Buffer (KA820) */
 130 #define PR_TXCS3  90 /* Serial-Line Unit 3 Transmit CSR (KA820) */
 131 #define PR_TXDB3  91 /* Serial-Line Unit 3 Transmit Data Buffer (KA820) */
 132 #define PR_RXCD   92 /* Receive Console Data from another CPU (KA820) */
 133 #define PR_CACHEX 93 /* Cache invalidate Register (KA820) */
 134 #define PR_BINID  94 /* VAXBI node ID Register (KA820) */
 135 #define PR_BISTOP 95 /* VAXBI Stop Register (KA820) */
 136
 137 #define PR_BCBTS  113 /* Backup Cache Tag Store (KA670) */
 138 #define PR_BCP1TS 114 /* Primary Tag Store 1st half (KA670) */
 139 #define PR_BCP2TS 115 /* Primary Tag Store 2st half (KA670) */
 140 #define PR_BCRFR  116 /* Refresh Register (KA670) */
 141 #define PR_BCIDX  117 /* Index Register (KA670) */
 142 #define PR_BCSTS  118 /* Status (KA670) */
 143 #define PR_BCCTL  119 /* Control Register (KA670) */
 144 #define PR_BCERR  120 /* Error Address (KA670) */
 145 #define PR_BCFBTS 121 /* Flush backup tag store (KA670) */
 146 #define PR_BCFPTS 122 /* Flush primary tag store (KA670) */
 147
 148 #define PR_VINTSR 123 /* vector i/f error status (KA43/KA46) */
 149 #define PR_PCTAG  124 /* primary cache tag store (KA43/KA46) */
 150 #define PR_PCIDX  125 /* primary cache index (KA43/KA46) */
 151 #define PR_PCERR  126 /* primary cache error address (KA43/KA46) */
 152 #define PR_PCSTS  127 /* primary cache status (KA43/KA46) */
 153
 154 #define PR_VPSR   144 /* Vector processor status register */
 155 #define PR_VAER   145 /* Vector arithmetic error register */
 156 #define PR_VMAC   146 /* Vector memory activity register */
 157 #define PR_VTBIA  147 /* Vector TBIA */
 158 #define PR_VSAR   148 /* Vector state address register */
 159 #define PR_VIADR  157 /* Vector indirect address register */
 160 #define PR_VIDLO  158 /* Vector indirect data low */
 161 #define PR_VIDHI  159 /* Vector indirect data high */
 162
 163 /* Definitions for AST */
 164 #define AST_NO    4
 165 #define AST_OK    3
 166
 167 #ifndef _LOCORE
 168
 169 static inline void
 170 mtpr(register_t val, int reg)
 171 {
 172         __asm volatile (
 173                 "mtpr %0,%1"
 174             : /* No output */
 175             : "g" (val), "g" (reg)
 176             : "memory");
 177 }
 178
 179 static inline register_t
 180 mfpr(int reg)
 181 {
 182         register_t __val;
 183         __asm volatile (
 184                 "mfpr %1,%0"
 185             : "=g" (__val)
 186             : "g" (reg));
 187         return __val;
 188 }
 189 #endif  /* _LOCORE */
 190
 191 #endif /* _VAX_MTPR_H_ */