sys/arch/x86/include/intrdefs.h

   1 /*      $NetBSD: intrdefs.h,v 1.14 2008/11/11 13:45:10 ad Exp $ */
   2
   3 #ifndef _X86_INTRDEFS_H_
   4 #define _X86_INTRDEFS_H_
   5
   6 /* Interrupt priority levels. */
   7 #define IPL_NONE        0x0     /* nothing */
   8 #define IPL_PREEMPT     0x1     /* fake, to prevent recursive preemptions */
   9 #define IPL_SOFTCLOCK   0x2     /* timeouts */
  10 #define IPL_SOFTBIO     0x3     /* block I/O passdown */
  11 #define IPL_SOFTNET     0x4     /* protocol stacks */
  12 #define IPL_SOFTSERIAL  0x5     /* serial passdown */
  13 #define IPL_VM          0x6     /* low I/O, memory allocation */
  14 #define IPL_SCHED       0x7     /* medium I/O, scheduler, clock */
  15 #define IPL_HIGH        0x8     /* high I/O, statclock, IPIs */
  16 #define NIPL            9
  17
  18 /* Interrupt sharing types. */
  19 #define IST_NONE        0       /* none */
  20 #define IST_PULSE       1       /* pulsed */
  21 #define IST_EDGE        2       /* edge-triggered */
  22 #define IST_LEVEL       3       /* level-triggered */
  23
  24 /*
  25  * Local APIC masks and software interrupt masks, in order
  26  * of priority.  Must not conflict with SIR_* below.
  27  */
  28 #define LIR_IPI         31
  29 #define LIR_TIMER       30
  30
  31 /*
  32  * XXX These should be lowest numbered, but right now would
  33  * conflict with the legacy IRQs.  Their current position
  34  * means that soft interrupt take priority over hardware
  35  * interrupts when lowering the priority level!
  36  */
  37 #define SIR_SERIAL      29
  38 #define SIR_NET         28
  39 #define SIR_BIO         27
  40 #define SIR_CLOCK       26
  41 #define SIR_PREEMPT     25
  42
  43 /*
  44  * Maximum # of interrupt sources per CPU. 32 to fit in one word.
  45  * ioapics can theoretically produce more, but it's not likely to
  46  * happen. For multiple ioapics, things can be routed to different
  47  * CPUs.
  48  */
  49 #define MAX_INTR_SOURCES        32
  50 #define NUM_LEGACY_IRQS         16
  51
  52 /*
  53  * Low and high boundaries between which interrupt gates will
  54  * be allocated in the IDT.
  55  */
  56 #define IDT_INTR_LOW    (0x20 + NUM_LEGACY_IRQS)
  57 #define IDT_INTR_HIGH   0xef
  58
  59 #define X86_IPI_HALT                    0x00000001
  60 #define X86_IPI_MICROSET                0x00000002
  61 #define X86_IPI__UNUSED1                0x00000004
  62 #define X86_IPI_SYNCH_FPU               0x00000008
  63 #define X86_IPI_MTRR                    0x00000010
  64 #define X86_IPI_GDT                     0x00000020
  65 #define X86_IPI__UNUSED2                0x00000040
  66 #define X86_IPI_ACPI_CPU_SLEEP          0x00000080
  67 #define X86_IPI_KPREEMPT                0x00000100
  68
  69 #define X86_NIPI                9
  70
  71 #define X86_IPI_NAMES { "halt IPI", "timeset IPI", "unused", \
  72                          "FPU synch IPI", "MTRR update IPI", \
  73                          "GDT update IPI", "unused", \
  74                          "ACPI CPU sleep IPI", "kpreempt IPI" }
  75
  76 #define IREENT_MAGIC    0x18041969
  77
  78 #endif /* _X86_INTRDEFS_H_ */