sys/arch/x86/include/specialreg.h

   1 /*      $NetBSD: specialreg.h,v 1.36 2009/05/26 01:42:02 rmind Exp $    */
   2
   3 /*-
   4  * Copyright (c) 1991 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of the University nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  *      @(#)specialreg.h        7.1 (Berkeley) 5/9/91
  32  */
  33
  34 /*
  35  * Bits in 386 special registers:
  36  */
  37 #define CR0_PE  0x00000001      /* Protected mode Enable */
  38 #define CR0_MP  0x00000002      /* "Math" Present (NPX or NPX emulator) */
  39 #define CR0_EM  0x00000004      /* EMulate non-NPX coproc. (trap ESC only) */
  40 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
  41 #define CR0_ET  0x00000010      /* Extension Type (387 (if set) vs 287) */
  42 #define CR0_PG  0x80000000      /* PaGing enable */
  43
  44 /*
  45  * Bits in 486 special registers:
  46  */
  47 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
  48 #define CR0_WP  0x00010000      /* Write Protect (honor PG_RW in all modes) */
  49 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
  50 #define CR0_NW  0x20000000      /* Not Write-through */
  51 #define CR0_CD  0x40000000      /* Cache Disable */
  52
  53 /*
  54  * Cyrix 486 DLC special registers, accessible as IO ports.
  55  */
  56 #define CCR0    0xc0            /* configuration control register 0 */
  57 #define CCR0_NC0        0x01    /* first 64K of each 1M memory region is non-cacheable */
  58 #define CCR0_NC1        0x02    /* 640K-1M region is non-cacheable */
  59 #define CCR0_A20M       0x04    /* enables A20M# input pin */
  60 #define CCR0_KEN        0x08    /* enables KEN# input pin */
  61 #define CCR0_FLUSH      0x10    /* enables FLUSH# input pin */
  62 #define CCR0_BARB       0x20    /* flushes internal cache when entering hold state */
  63 #define CCR0_CO         0x40    /* cache org: 1=direct mapped, 0=2x set assoc */
  64 #define CCR0_SUSPEND    0x80    /* enables SUSP# and SUSPA# pins */
  65
  66 #define CCR1    0xc1            /* configuration control register 1 */
  67 #define CCR1_RPL        0x01    /* enables RPLSET and RPLVAL# pins */
  68 /* the remaining 7 bits of this register are reserved */
  69
  70 /*
  71  * bits in the pentiums %cr4 register:
  72  */
  73
  74 #define CR4_VME 0x00000001      /* virtual 8086 mode extension enable */
  75 #define CR4_PVI 0x00000002      /* protected mode virtual interrupt enable */
  76 #define CR4_TSD 0x00000004      /* restrict RDTSC instruction to cpl 0 only */
  77 #define CR4_DE  0x00000008      /* debugging extension */
  78 #define CR4_PSE 0x00000010      /* large (4MB) page size enable */
  79 #define CR4_PAE 0x00000020      /* physical address extension enable */
  80 #define CR4_MCE 0x00000040      /* machine check enable */
  81 #define CR4_PGE 0x00000080      /* page global enable */
  82 #define CR4_PCE 0x00000100      /* enable RDPMC instruction for all cpls */
  83 #define CR4_OSFXSR      0x00000200      /* enable fxsave/fxrestor and SSE */
  84 #define CR4_OSXMMEXCPT  0x00000400      /* enable unmasked SSE exceptions */
  85
  86 /*
  87  * CPUID "features" bits in %edx
  88  */
  89
  90 /* Fn80000001 %edx feature */
  91 #define CPUID_FPU       0x00000001      /* processor has an FPU? */
  92 #define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */
  93 #define CPUID_DE        0x00000004      /* has debugging extension */
  94 #define CPUID_PSE       0x00000008      /* has page 4MB page size extension */
  95 #define CPUID_TSC       0x00000010      /* has time stamp counter */
  96 #define CPUID_MSR       0x00000020      /* has mode specific registers */
  97 #define CPUID_PAE       0x00000040      /* has phys address extension */
  98 #define CPUID_MCE       0x00000080      /* has machine check exception */
  99 #define CPUID_CX8       0x00000100      /* has CMPXCHG8B instruction */
 100 #define CPUID_APIC      0x00000200      /* has enabled APIC */
 101 #define CPUID_B10       0x00000400      /* reserved, MTRR */
 102 #define CPUID_SEP       0x00000800      /* has SYSENTER/SYSEXIT extension */
 103 #define CPUID_MTRR      0x00001000      /* has memory type range register */
 104 #define CPUID_PGE       0x00002000      /* has page global extension */
 105 #define CPUID_MCA       0x00004000      /* has machine check architecture */
 106 #define CPUID_CMOV      0x00008000      /* has CMOVcc instruction */
 107 #define CPUID_PAT       0x00010000      /* Page Attribute Table */
 108 #define CPUID_PSE36     0x00020000      /* 36-bit PSE */
 109 #define CPUID_PN        0x00040000      /* processor serial number */
 110 #define CPUID_CFLUSH    0x00080000      /* CFLUSH insn supported */
 111 #define CPUID_B20       0x00100000      /* reserved */
 112 #define CPUID_DS        0x00200000      /* Debug Store */
 113 #define CPUID_ACPI      0x00400000      /* ACPI performance modulation regs */
 114 #define CPUID_MMX       0x00800000      /* MMX supported */
 115 #define CPUID_FXSR      0x01000000      /* fast FP/MMX save/restore */
 116 #define CPUID_SSE       0x02000000      /* streaming SIMD extensions */
 117 #define CPUID_SSE2      0x04000000      /* streaming SIMD extensions #2 */
 118 #define CPUID_SS        0x08000000      /* self-snoop */
 119 #define CPUID_HTT       0x10000000      /* Hyper-Threading Technology */
 120 #define CPUID_TM        0x20000000      /* thermal monitor (TCC) */
 121 #define CPUID_IA64      0x40000000      /* IA-64 architecture */
 122 #define CPUID_SBF       0x80000000      /* signal break on FERR */
 123
 124 #define CPUID_FLAGS1    "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8" \
 125                             "\12APIC\13B10\14SEP\15MTRR\16PGE\17MCA\20CMOV" \
 126                             "\21PAT\22PSE36\23PN\24CFLUSH\25B20\26DS\27ACPI" \
 127                             "\30MMX\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM" \
 128                             "\37IA64\40SBF"
 129
 130 /*
 131  * CPUID Intel extended features - %EDX
 132  */
 133 #define CPUID_SYSCALL   0x00000800      /* SYSCALL/SYSRET */
 134 #define CPUID_XD        0x00100000      /* Execute Disable */
 135 #define CPUID_EM64T     0x20000000      /* Intel EM64T */
 136
 137 #define CPUID_INTEL_EXT_FLAGS   "\20\14SYSCALL/SYSRET\25XD\36EM64T"
 138
 139 /*
 140  * CPUID Intel extended features - %ECX
 141  */
 142 #define CPUID_LAHF      0x00000001      /* LAHF/SAHF in IA-32e mode, 64bit sub*/
 143
 144 #define CPUID_INTEL_FLAGS4      "\20\1LAHF"
 145
 146 /*
 147  * AMD/VIA processor specific flags.
 148  */
 149
 150 /*      CPUID_SYSCALL                      SYSCALL/SYSRET */
 151 #define CPUID_MPC       0x00080000      /* Multiprocessing Capable */
 152 #define CPUID_NOX       0x00100000      /* No Execute Page Protection */
 153 #define CPUID_MMXX      0x00400000      /* AMD MMX Extensions */
 154 #define CPUID_FFXSR     0x02000000      /* FXSAVE/FXSTOR Extensions */
 155 #define CPUID_P1GB      0x04000000      /* 1GB Large Page Support */
 156 #define CPUID_RDTSCP    0x08000000      /* Read TSC Pair Instruction */
 157 /*      CPUID_EM64T                        Long mode */
 158 #define CPUID_3DNOW2    0x40000000      /* 3DNow! Instruction Extension */
 159 #define CPUID_3DNOW     0x80000000      /* 3DNow! Instructions */
 160
 161 #define CPUID_EXT_FLAGS "\20\14SYSCALL/SYSRET\24MPC\25NOX\27MXX\32FFXSR" \
 162                             "\33P1GB\34RDTSCP\36LONG\0373DNOW2\0403DNOW"
 163
 164
 165 /* AMD Fn80000001 %ecx features */
 166 #define CPUID_LAHF      0x00000001      /* LAHF/SAHF instruction */
 167 #define CPUID_CMPLEGACY 0x00000002      /* Compare Legacy */
 168 #define CPUID_SVM       0x00000004      /* Secure Virtual Machine */
 169 #define CPUID_EAPIC     0x00000008      /* Extended APIC space */
 170 #define CPUID_ALTMOVCR0 0x00000010      /* Lock Mov Cr0 */
 171 #define CPUID_LZCNT     0x00000020      /* LZCNT instruction */
 172 #define CPUID_SSE4A     0x00000040      /* SSE4A instruction set */
 173 #define CPUID_MISALIGNSSE 0x00000080    /* Misaligned SSE */
 174 #define CPUID_3DNOWPF   0x00000100      /* 3DNow Prefetch */
 175 #define CPUID_OSVW      0x00000200      /* OS visible workarounds */
 176 #define CPUID_IBS       0x00000400      /* Instruction Based Sampling */
 177 #define CPUID_SSE5      0x00000800      /* SSE5 instruction set */
 178 #define CPUID_SKINIT    0x00001000      /* SKINIT */
 179 #define CPUID_WDT       0x00002000      /* watchdog timer support */
 180
 181 #define CPUID_AMD_FLAGS4        "\20\1LAHF\2CMPLEGACY\3SVM\4EAPIC\5ALTMOVCR0" \
 182                                     "\6LZCNT\7SSE4A\10MISALIGNSSE" \
 183                                     "\0113DNOWPREFETCH\12OSVW\13IBS" \
 184                                     "\14SSE5\15SKINIT\16WDT"
 185
 186 /* AMD Fn8000000a %edx features (SVM features) */
 187 #define CPUID_AMD_SVM_NP                0x00000001
 188 #define CPUID_AMD_SVM_LbrVirt           0x00000002
 189 #define CPUID_AMD_SVM_SVML              0x00000004
 190 #define CPUID_AMD_SVM_NRIPS             0x00000008
 191 #define CPUID_AMD_SVM_Ssse3Sse5Dis      0x00000200
 192 #define CPUID_AMD_SVM_FLAGS      "\20\1NP\2LbrVirt\3SVML\4NRIPS\12Ssse3Sse5Dis"
 193
 194 /*
 195  * AMD Advanced Power Management
 196  * CPUID Fn8000_0007 %edx
 197  */
 198
 199 #define CPUID_APM_TS    0x00000001      /* Temperature Sensor */
 200 #define CPUID_APM_FID   0x00000002      /* Frequency ID control */
 201 #define CPUID_APM_VID   0x00000004      /* Voltage ID control */
 202 #define CPUID_APM_TTP   0x00000008      /* THERMTRIP (PCI F3xE4 register) */
 203 #define CPUID_APM_HTC   0x00000010      /* Hardware thermal control (HTC) */
 204 #define CPUID_APM_STC   0x00000020      /* Software thermal control (STC) */
 205 #define CPUID_APM_100   0x00000040      /* 100MHz multiplier control */
 206 #define CPUID_APM_HWP   0x00000080      /* HW P-State control */
 207 #define CPUID_APM_TSC   0x00000100      /* TSC invariant */
 208
 209 #define CPUID_APM_FLAGS         "\20\1TS\2FID\3VID\4TTP\5HTC\6STC\007100" \
 210                                     "\10HWP\11TSC"
 211
 212 /*
 213  * Centaur Extended Feature flags
 214  */
 215 #define CPUID_VIA_HAS_RNG       0x00000004      /* Random number generator */
 216 #define CPUID_VIA_DO_RNG        0x00000008
 217 #define CPUID_VIA_HAS_ACE       0x00000040      /* AES Encryption */
 218 #define CPUID_VIA_DO_ACE        0x00000080
 219 #define CPUID_VIA_HAS_ACE2      0x00000100      /* AES+CTR instructions */
 220 #define CPUID_VIA_DO_ACE2       0x00000200
 221 #define CPUID_VIA_HAS_PHE       0x00000400      /* SHA1+SHA256 HMAC */
 222 #define CPUID_VIA_DO_PHE        0x00000800
 223 #define CPUID_VIA_HAS_PMM       0x00001000      /* RSA Instructions */
 224 #define CPUID_VIA_DO_PMM        0x00002000
 225
 226 #define CPUID_FLAGS_PADLOCK     "\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA"
 227
 228 /*
 229  * CPUID "features" bits in Fn00000001 %ecx
 230  */
 231
 232 #define CPUID2_SSE3     0x00000001      /* Streaming SIMD Extensions 3 */
 233 #define CPUID2_DTES64   0x00000004      /* 64-bit Debug Trace */
 234 #define CPUID2_MONITOR  0x00000008      /* MONITOR/MWAIT instructions */
 235 #define CPUID2_DS_CPL   0x00000010      /* CPL Qualified Debug Store */
 236 #define CPUID2_VMX      0x00000020      /* Virtual Machine Extensions */
 237 #define CPUID2_SMX      0x00000040      /* Safer Mode Extensions */
 238 #define CPUID2_EST      0x00000080      /* Enhanced SpeedStep Technology */
 239 #define CPUID2_TM2      0x00000100      /* Thermal Monitor 2 */
 240 #define CPUID2_SSSE3    0x00000200      /* Supplemental SSE3 */
 241 #define CPUID2_CID      0x00000400      /* Context ID */
 242 #define CPUID2_CX16     0x00002000      /* has CMPXCHG16B instruction */
 243 #define CPUID2_xTPR     0x00004000      /* Task Priority Messages disabled? */
 244 #define CPUID2_PDCM     0x00008000      /* Perf/Debug Capability MSR */
 245 #define CPUID2_DCA      0x00040000      /* Direct Cache Access */
 246 #define CPUID2_SSE41    0x00080000      /* Streaming SIMD Extensions 4.1 */
 247 #define CPUID2_SSE42    0x00100000      /* Streaming SIMD Extensions 4.2 */
 248 #define CPUID2_X2APIC   0x00200000      /* xAPIC Extensions */
 249 #define CPUID2_POPCNT   0x00800000      /* popcount instruction available */
 250 #define CPUID2_RAZ      0x80000000      /* RAZ. Indicates guest state. */
 251
 252 #define CPUID2_FLAGS1   "\20\1SSE3\2B01\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX" \
 253                             "\10EST\11TM2\12SSSE3\13CID\14B11\15B12\16CX16" \
 254                             "\17xTPR\20PDCM\21B16\22B17\23DCA\24SSE41\25SSE42" \
 255                             "\26X2APIC\27MOVBE\30POPCNT\31B24\32B25\33XSAVE" \
 256                             "\34OSXSAVE\35B28\36B29\37B30\40RAZ"
 257
 258 #define CPUID2FAMILY(cpuid)     (((cpuid) >> 8) & 0xf)
 259 #define CPUID2MODEL(cpuid)      (((cpuid) >> 4) & 0xf)
 260 #define CPUID2STEPPING(cpuid)   ((cpuid) & 0xf)
 261
 262 /* Extended family and model are defined on amd64 processors */
 263 #define CPUID2EXTFAMILY(cpuid)  (((cpuid) >> 20) & 0xff)
 264 #define CPUID2EXTMODEL(cpuid)   (((cpuid) >> 16) & 0xf)
 265
 266 /*
 267  * Model-specific registers for the i386 family
 268  */
 269 #define MSR_P5_MC_ADDR          0x000   /* P5 only */
 270 #define MSR_P5_MC_TYPE          0x001   /* P5 only */
 271 #define MSR_TSC                 0x010
 272 #define MSR_CESR                0x011   /* P5 only (trap on P6) */
 273 #define MSR_CTR0                0x012   /* P5 only (trap on P6) */
 274 #define MSR_CTR1                0x013   /* P5 only (trap on P6) */
 275 #define MSR_APICBASE            0x01b
 276 #define MSR_EBL_CR_POWERON      0x02a
 277 #define MSR_EBC_FREQUENCY_ID    0x02c   /* PIV only */
 278 #define MSR_TEST_CTL            0x033
 279 #define MSR_BIOS_UPDT_TRIG      0x079
 280 #define MSR_BBL_CR_D0           0x088   /* PII+ only */
 281 #define MSR_BBL_CR_D1           0x089   /* PII+ only */
 282 #define MSR_BBL_CR_D2           0x08a   /* PII+ only */
 283 #define MSR_BIOS_SIGN           0x08b
 284 #define MSR_PERFCTR0            0x0c1
 285 #define MSR_PERFCTR1            0x0c2
 286 #define MSR_FSB_FREQ            0x0cd   /* Core Duo/Solo only */
 287 #define MSR_IA32_EXT_CONFIG     0x0ee   /* Undocumented. Core Solo/Duo only */
 288 #define MSR_MTRRcap             0x0fe
 289 #define MSR_BBL_CR_ADDR         0x116   /* PII+ only */
 290 #define MSR_BBL_CR_DECC         0x118   /* PII+ only */
 291 #define MSR_BBL_CR_CTL          0x119   /* PII+ only */
 292 #define MSR_BBL_CR_TRIG         0x11a   /* PII+ only */
 293 #define MSR_BBL_CR_BUSY         0x11b   /* PII+ only */
 294 #define MSR_BBL_CR_CTR3         0x11e   /* PII+ only */
 295 #define MSR_SYSENTER_CS         0x174   /* PII+ only */
 296 #define MSR_SYSENTER_ESP        0x175   /* PII+ only */
 297 #define MSR_SYSENTER_EIP        0x176   /* PII+ only */
 298 #define MSR_MCG_CAP             0x179
 299 #define MSR_MCG_STATUS          0x17a
 300 #define MSR_MCG_CTL             0x17b
 301 #define MSR_EVNTSEL0            0x186
 302 #define MSR_EVNTSEL1            0x187
 303 #define MSR_PERF_STATUS         0x198   /* Pentium M */
 304 #define MSR_PERF_CTL            0x199   /* Pentium M */
 305 #define MSR_THERM_CONTROL       0x19a
 306 #define MSR_THERM_INTERRUPT     0x19b
 307 #define MSR_THERM_STATUS        0x19c
 308 #define MSR_THERM2_CTL          0x19d   /* Pentium M */
 309 #define MSR_MISC_ENABLE         0x1a0
 310 #define MSR_DEBUGCTLMSR         0x1d9
 311 #define MSR_LASTBRANCHFROMIP    0x1db
 312 #define MSR_LASTBRANCHTOIP      0x1dc
 313 #define MSR_LASTINTFROMIP       0x1dd
 314 #define MSR_LASTINTTOIP         0x1de
 315 #define MSR_ROB_CR_BKUPTMPDR6   0x1e0
 316 #define MSR_MTRRphysBase0       0x200
 317 #define MSR_MTRRphysMask0       0x201
 318 #define MSR_MTRRphysBase1       0x202
 319 #define MSR_MTRRphysMask1       0x203
 320 #define MSR_MTRRphysBase2       0x204
 321 #define MSR_MTRRphysMask2       0x205
 322 #define MSR_MTRRphysBase3       0x206
 323 #define MSR_MTRRphysMask3       0x207
 324 #define MSR_MTRRphysBase4       0x208
 325 #define MSR_MTRRphysMask4       0x209
 326 #define MSR_MTRRphysBase5       0x20a
 327 #define MSR_MTRRphysMask5       0x20b
 328 #define MSR_MTRRphysBase6       0x20c
 329 #define MSR_MTRRphysMask6       0x20d
 330 #define MSR_MTRRphysBase7       0x20e
 331 #define MSR_MTRRphysMask7       0x20f
 332 #define MSR_MTRRfix64K_00000    0x250
 333 #define MSR_MTRRfix16K_80000    0x258
 334 #define MSR_MTRRfix16K_A0000    0x259
 335 #define MSR_MTRRfix4K_C0000     0x268
 336 #define MSR_MTRRfix4K_C8000     0x269
 337 #define MSR_MTRRfix4K_D0000     0x26a
 338 #define MSR_MTRRfix4K_D8000     0x26b
 339 #define MSR_MTRRfix4K_E0000     0x26c
 340 #define MSR_MTRRfix4K_E8000     0x26d
 341 #define MSR_MTRRfix4K_F0000     0x26e
 342 #define MSR_MTRRfix4K_F8000     0x26f
 343 #define MSR_MTRRdefType         0x2ff
 344 #define MSR_MC0_CTL             0x400
 345 #define MSR_MC0_STATUS          0x401
 346 #define MSR_MC0_ADDR            0x402
 347 #define MSR_MC0_MISC            0x403
 348 #define MSR_MC1_CTL             0x404
 349 #define MSR_MC1_STATUS          0x405
 350 #define MSR_MC1_ADDR            0x406
 351 #define MSR_MC1_MISC            0x407
 352 #define MSR_MC2_CTL             0x408
 353 #define MSR_MC2_STATUS          0x409
 354 #define MSR_MC2_ADDR            0x40a
 355 #define MSR_MC2_MISC            0x40b
 356 #define MSR_MC4_CTL             0x40c
 357 #define MSR_MC4_STATUS          0x40d
 358 #define MSR_MC4_ADDR            0x40e
 359 #define MSR_MC4_MISC            0x40f
 360 #define MSR_MC3_CTL             0x410
 361 #define MSR_MC3_STATUS          0x411
 362 #define MSR_MC3_ADDR            0x412
 363 #define MSR_MC3_MISC            0x413
 364
 365 /*
 366  * VIA "Nehemiah" MSRs
 367  */
 368 #define MSR_VIA_RNG             0x0000110b
 369 #define MSR_VIA_RNG_ENABLE      0x00000040
 370 #define MSR_VIA_RNG_NOISE_MASK  0x00000300
 371 #define MSR_VIA_RNG_NOISE_A     0x00000000
 372 #define MSR_VIA_RNG_NOISE_B     0x00000100
 373 #define MSR_VIA_RNG_2NOISE      0x00000300
 374 #define MSR_VIA_ACE             0x00001107
 375 #define MSR_VIA_ACE_ENABLE      0x10000000
 376
 377 /*
 378  * AMD K6/K7 MSRs.
 379  */
 380 #define MSR_K6_UWCCR            0xc0000085
 381 #define MSR_K7_EVNTSEL0         0xc0010000
 382 #define MSR_K7_EVNTSEL1         0xc0010001
 383 #define MSR_K7_EVNTSEL2         0xc0010002
 384 #define MSR_K7_EVNTSEL3         0xc0010003
 385 #define MSR_K7_PERFCTR0         0xc0010004
 386 #define MSR_K7_PERFCTR1         0xc0010005
 387 #define MSR_K7_PERFCTR2         0xc0010006
 388 #define MSR_K7_PERFCTR3         0xc0010007
 389
 390 /*
 391  * AMD K8 (Opteron) MSRs.
 392  */
 393 #define MSR_SYSCFG      0xc0000010
 394
 395 #define MSR_EFER        0xc0000080              /* Extended feature enable */
 396 #define         EFER_SCE                0x00000001      /* SYSCALL extension */
 397 #define         EFER_LME                0x00000100      /* Long Mode Active */
 398 #define         EFER_LMA                0x00000400      /* Long Mode Enabled */
 399 #define         EFER_NXE                0x00000800      /* No-Execute Enabled */
 400
 401 #define MSR_STAR        0xc0000081              /* 32 bit syscall gate addr */
 402 #define MSR_LSTAR       0xc0000082              /* 64 bit syscall gate addr */
 403 #define MSR_CSTAR       0xc0000083              /* compat syscall gate addr */
 404 #define MSR_SFMASK      0xc0000084              /* flags to clear on syscall */
 405
 406 #define MSR_FSBASE      0xc0000100              /* 64bit offset for fs: */
 407 #define MSR_GSBASE      0xc0000101              /* 64bit offset for gs: */
 408 #define MSR_KERNELGSBASE 0xc0000102             /* storage for swapgs ins */
 409
 410 #define MSR_VMCR        0xc0010114      /* Virtual Machine Control Register */
 411 #define         VMCR_DPD        0x00000001      /* Debug port disable */
 412 #define         VMCR_RINIT      0x00000002      /* intercept init */
 413 #define         VMCR_DISA20     0x00000004      /* Disable A20 masking */
 414 #define         VMCR_LOCK       0x00000008      /* SVM Lock */
 415 #define         VMCR_SVMED      0x00000010      /* SVME Disable */
 416 #define MSR_SVMLOCK     0xc0010118      /* SVM Lock key */
 417
 418 /*
 419  * These require a 'passcode' for access.  See cpufunc.h.
 420  */
 421 #define MSR_HWCR        0xc0010015
 422 #define         HWCR_TLBCACHEDIS        0x00000008
 423 #define         HWCR_FFDIS              0x00000040
 424
 425 #define MSR_NB_CFG      0xc001001f
 426 #define         NB_CFG_DISIOREQLOCK     0x0000000000000004ULL
 427 #define         NB_CFG_DISDATMSK        0x0000001000000000ULL
 428 #define         NB_CFG_INITAPICCPUIDLO  (1ULL << 54)
 429
 430 #define MSR_LS_CFG      0xc0011020
 431 #define         LS_CFG_DIS_LS2_SQUISH   0x02000000
 432
 433 #define MSR_IC_CFG      0xc0011021
 434 #define         IC_CFG_DIS_SEQ_PREFETCH 0x00000800
 435
 436 #define MSR_DC_CFG      0xc0011022
 437 #define         DC_CFG_DIS_CNV_WC_SSO   0x00000004
 438 #define         DC_CFG_DIS_SMC_CHK_BUF  0x00000400
 439 #define         DC_CFG_ERRATA_261       0x01000000
 440
 441 #define MSR_BU_CFG      0xc0011023
 442 #define         BU_CFG_ERRATA_298       0x0000000000000002ULL
 443 #define         BU_CFG_ERRATA_254       0x0000000000200000ULL
 444 #define         BU_CFG_ERRATA_309       0x0000000000800000ULL
 445 #define         BU_CFG_THRL2IDXCMPDIS   0x0000080000000000ULL
 446 #define         BU_CFG_WBPFSMCCHKDIS    0x0000200000000000ULL
 447 #define         BU_CFG_WBENHWSBDIS      0x0001000000000000ULL
 448
 449 /*
 450  * Constants related to MTRRs
 451  */
 452 #define MTRR_N64K               8       /* numbers of fixed-size entries */
 453 #define MTRR_N16K               16
 454 #define MTRR_N4K                64
 455
 456 /*
 457  * the following four 3-byte registers control the non-cacheable regions.
 458  * These registers must be written as three separate bytes.
 459  *
 460  * NCRx+0: A31-A24 of starting address
 461  * NCRx+1: A23-A16 of starting address
 462  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
 463  *
 464  * The non-cacheable region's starting address must be aligned to the
 465  * size indicated by the NCR_SIZE_xx field.
 466  */
 467 #define NCR1    0xc4
 468 #define NCR2    0xc7
 469 #define NCR3    0xca
 470 #define NCR4    0xcd
 471
 472 #define NCR_SIZE_0K     0
 473 #define NCR_SIZE_4K     1
 474 #define NCR_SIZE_8K     2
 475 #define NCR_SIZE_16K    3
 476 #define NCR_SIZE_32K    4
 477 #define NCR_SIZE_64K    5
 478 #define NCR_SIZE_128K   6
 479 #define NCR_SIZE_256K   7
 480 #define NCR_SIZE_512K   8
 481 #define NCR_SIZE_1M     9
 482 #define NCR_SIZE_2M     10
 483 #define NCR_SIZE_4M     11
 484 #define NCR_SIZE_8M     12
 485 #define NCR_SIZE_16M    13
 486 #define NCR_SIZE_32M    14
 487 #define NCR_SIZE_4G     15
 488
 489 /*
 490  * Performance monitor events.
 491  *
 492  * Note that 586-class and 686-class CPUs have different performance
 493  * monitors available, and they are accessed differently:
 494  *
 495  *      686-class: `rdpmc' instruction
 496  *      586-class: `rdmsr' instruction, CESR MSR
 497  *
 498  * The descriptions of these events are too lenghy to include here.
 499  * See Appendix A of "Intel Architecture Software Developer's
 500  * Manual, Volume 3: System Programming" for more information.
 501  */
 502
 503 /*
 504  * 586-class CESR MSR format.  Lower 16 bits is CTR0, upper 16 bits
 505  * is CTR1.
 506  */
 507
 508 #define PMC5_CESR_EVENT                 0x003f
 509 #define PMC5_CESR_OS                    0x0040
 510 #define PMC5_CESR_USR                   0x0080
 511 #define PMC5_CESR_E                     0x0100
 512 #define PMC5_CESR_P                     0x0200
 513
 514 #define PMC5_DATA_READ                  0x00
 515 #define PMC5_DATA_WRITE                 0x01
 516 #define PMC5_DATA_TLB_MISS              0x02
 517 #define PMC5_DATA_READ_MISS             0x03
 518 #define PMC5_DATA_WRITE_MISS            0x04
 519 #define PMC5_WRITE_M_E                  0x05
 520 #define PMC5_DATA_LINES_WBACK           0x06
 521 #define PMC5_DATA_CACHE_SNOOP           0x07
 522 #define PMC5_DATA_CACHE_SNOOP_HIT       0x08
 523 #define PMC5_MEM_ACCESS_BOTH_PIPES      0x09
 524 #define PMC5_BANK_CONFLICTS             0x0a
 525 #define PMC5_MISALIGNED_DATA            0x0b
 526 #define PMC5_INST_READ                  0x0c
 527 #define PMC5_INST_TLB_MISS              0x0d
 528 #define PMC5_INST_CACHE_MISS            0x0e
 529 #define PMC5_SEGMENT_REG_LOAD           0x0f
 530 #define PMC5_BRANCHES                   0x12
 531 #define PMC5_BTB_HITS                   0x13
 532 #define PMC5_BRANCH_TAKEN               0x14
 533 #define PMC5_PIPELINE_FLUSH             0x15
 534 #define PMC5_INST_EXECUTED              0x16
 535 #define PMC5_INST_EXECUTED_V_PIPE       0x17
 536 #define PMC5_BUS_UTILIZATION            0x18
 537 #define PMC5_WRITE_BACKUP_STALL         0x19
 538 #define PMC5_DATA_READ_STALL            0x1a
 539 #define PMC5_WRITE_E_M_STALL            0x1b
 540 #define PMC5_LOCKED_BUS                 0x1c
 541 #define PMC5_IO_CYCLE                   0x1d
 542 #define PMC5_NONCACHE_MEM_READ          0x1e
 543 #define PMC5_AGI_STALL                  0x1f
 544 #define PMC5_FLOPS                      0x22
 545 #define PMC5_BP0_MATCH                  0x23
 546 #define PMC5_BP1_MATCH                  0x24
 547 #define PMC5_BP2_MATCH                  0x25
 548 #define PMC5_BP3_MATCH                  0x26
 549 #define PMC5_HARDWARE_INTR              0x27
 550 #define PMC5_DATA_RW                    0x28
 551 #define PMC5_DATA_RW_MISS               0x29
 552
 553 /*
 554  * 686-class Event Selector MSR format.
 555  */
 556
 557 #define PMC6_EVTSEL_EVENT               0x000000ff
 558 #define PMC6_EVTSEL_UNIT                0x0000ff00
 559 #define PMC6_EVTSEL_UNIT_SHIFT          8
 560 #define PMC6_EVTSEL_USR                 (1 << 16)
 561 #define PMC6_EVTSEL_OS                  (1 << 17)
 562 #define PMC6_EVTSEL_E                   (1 << 18)
 563 #define PMC6_EVTSEL_PC                  (1 << 19)
 564 #define PMC6_EVTSEL_INT                 (1 << 20)
 565 #define PMC6_EVTSEL_EN                  (1 << 22)       /* PerfEvtSel0 only */
 566 #define PMC6_EVTSEL_INV                 (1 << 23)
 567 #define PMC6_EVTSEL_COUNTER_MASK        0xff000000
 568 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT  24
 569
 570 /* Data Cache Unit */
 571 #define PMC6_DATA_MEM_REFS              0x43
 572 #define PMC6_DCU_LINES_IN               0x45
 573 #define PMC6_DCU_M_LINES_IN             0x46
 574 #define PMC6_DCU_M_LINES_OUT            0x47
 575 #define PMC6_DCU_MISS_OUTSTANDING       0x48
 576
 577 /* Instruction Fetch Unit */
 578 #define PMC6_IFU_IFETCH                 0x80
 579 #define PMC6_IFU_IFETCH_MISS            0x81
 580 #define PMC6_ITLB_MISS                  0x85
 581 #define PMC6_IFU_MEM_STALL              0x86
 582 #define PMC6_ILD_STALL                  0x87
 583
 584 /* L2 Cache */
 585 #define PMC6_L2_IFETCH                  0x28
 586 #define PMC6_L2_LD                      0x29
 587 #define PMC6_L2_ST                      0x2a
 588 #define PMC6_L2_LINES_IN                0x24
 589 #define PMC6_L2_LINES_OUT               0x26
 590 #define PMC6_L2_M_LINES_INM             0x25
 591 #define PMC6_L2_M_LINES_OUTM            0x27
 592 #define PMC6_L2_RQSTS                   0x2e
 593 #define PMC6_L2_ADS                     0x21
 594 #define PMC6_L2_DBUS_BUSY               0x22
 595 #define PMC6_L2_DBUS_BUSY_RD            0x23
 596
 597 /* External Bus Logic */
 598 #define PMC6_BUS_DRDY_CLOCKS            0x62
 599 #define PMC6_BUS_LOCK_CLOCKS            0x63
 600 #define PMC6_BUS_REQ_OUTSTANDING        0x60
 601 #define PMC6_BUS_TRAN_BRD               0x65
 602 #define PMC6_BUS_TRAN_RFO               0x66
 603 #define PMC6_BUS_TRANS_WB               0x67
 604 #define PMC6_BUS_TRAN_IFETCH            0x68
 605 #define PMC6_BUS_TRAN_INVAL             0x69
 606 #define PMC6_BUS_TRAN_PWR               0x6a
 607 #define PMC6_BUS_TRANS_P                0x6b
 608 #define PMC6_BUS_TRANS_IO               0x6c
 609 #define PMC6_BUS_TRAN_DEF               0x6d
 610 #define PMC6_BUS_TRAN_BURST             0x6e
 611 #define PMC6_BUS_TRAN_ANY               0x70
 612 #define PMC6_BUS_TRAN_MEM               0x6f
 613 #define PMC6_BUS_DATA_RCV               0x64
 614 #define PMC6_BUS_BNR_DRV                0x61
 615 #define PMC6_BUS_HIT_DRV                0x7a
 616 #define PMC6_BUS_HITM_DRDV              0x7b
 617 #define PMC6_BUS_SNOOP_STALL            0x7e
 618
 619 /* Floating Point Unit */
 620 #define PMC6_FLOPS                      0xc1
 621 #define PMC6_FP_COMP_OPS_EXE            0x10
 622 #define PMC6_FP_ASSIST                  0x11
 623 #define PMC6_MUL                        0x12
 624 #define PMC6_DIV                        0x12
 625 #define PMC6_CYCLES_DIV_BUSY            0x14
 626
 627 /* Memory Ordering */
 628 #define PMC6_LD_BLOCKS                  0x03
 629 #define PMC6_SB_DRAINS                  0x04
 630 #define PMC6_MISALIGN_MEM_REF           0x05
 631 #define PMC6_EMON_KNI_PREF_DISPATCHED   0x07    /* P-III only */
 632 #define PMC6_EMON_KNI_PREF_MISS         0x4b    /* P-III only */
 633
 634 /* Instruction Decoding and Retirement */
 635 #define PMC6_INST_RETIRED               0xc0
 636 #define PMC6_UOPS_RETIRED               0xc2
 637 #define PMC6_INST_DECODED               0xd0
 638 #define PMC6_EMON_KNI_INST_RETIRED      0xd8
 639 #define PMC6_EMON_KNI_COMP_INST_RET     0xd9
 640
 641 /* Interrupts */
 642 #define PMC6_HW_INT_RX                  0xc8
 643 #define PMC6_CYCLES_INT_MASKED          0xc6
 644 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
 645
 646 /* Branches */
 647 #define PMC6_BR_INST_RETIRED            0xc4
 648 #define PMC6_BR_MISS_PRED_RETIRED       0xc5
 649 #define PMC6_BR_TAKEN_RETIRED           0xc9
 650 #define PMC6_BR_MISS_PRED_TAKEN_RET     0xca
 651 #define PMC6_BR_INST_DECODED            0xe0
 652 #define PMC6_BTB_MISSES                 0xe2
 653 #define PMC6_BR_BOGUS                   0xe4
 654 #define PMC6_BACLEARS                   0xe6
 655
 656 /* Stalls */
 657 #define PMC6_RESOURCE_STALLS            0xa2
 658 #define PMC6_PARTIAL_RAT_STALLS         0xd2
 659
 660 /* Segment Register Loads */
 661 #define PMC6_SEGMENT_REG_LOADS          0x06
 662
 663 /* Clocks */
 664 #define PMC6_CPU_CLK_UNHALTED           0x79
 665
 666 /* MMX Unit */
 667 #define PMC6_MMX_INSTR_EXEC             0xb0    /* Celeron, P-II, P-IIX only */
 668 #define PMC6_MMX_SAT_INSTR_EXEC         0xb1    /* P-II and P-III only */
 669 #define PMC6_MMX_UOPS_EXEC              0xb2    /* P-II and P-III only */
 670 #define PMC6_MMX_INSTR_TYPE_EXEC        0xb3    /* P-II and P-III only */
 671 #define PMC6_FP_MMX_TRANS               0xcc    /* P-II and P-III only */
 672 #define PMC6_MMX_ASSIST                 0xcd    /* P-II and P-III only */
 673 #define PMC6_MMX_INSTR_RET              0xc3    /* P-II only */
 674
 675 /* Segment Register Renaming */
 676 #define PMC6_SEG_RENAME_STALLS          0xd4    /* P-II and P-III only */
 677 #define PMC6_SEG_REG_RENAMES            0xd5    /* P-II and P-III only */
 678 #define PMC6_RET_SEG_RENAMES            0xd6    /* P-II and P-III only */
 679
 680 /*
 681  * AMD K7 Event Selector MSR format.
 682  */
 683
 684 #define K7_EVTSEL_EVENT                 0x000000ff
 685 #define K7_EVTSEL_UNIT                  0x0000ff00
 686 #define K7_EVTSEL_UNIT_SHIFT            8
 687 #define K7_EVTSEL_USR                   (1 << 16)
 688 #define K7_EVTSEL_OS                    (1 << 17)
 689 #define K7_EVTSEL_E                     (1 << 18)
 690 #define K7_EVTSEL_PC                    (1 << 19)
 691 #define K7_EVTSEL_INT                   (1 << 20)
 692 #define K7_EVTSEL_EN                    (1 << 22)
 693 #define K7_EVTSEL_INV                   (1 << 23)
 694 #define K7_EVTSEL_COUNTER_MASK          0xff000000
 695 #define K7_EVTSEL_COUNTER_MASK_SHIFT    24
 696
 697 /* Segment Register Loads */
 698 #define K7_SEGMENT_REG_LOADS            0x20
 699
 700 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
 701
 702 /* Data Cache Unit */
 703 #define K7_DATA_CACHE_ACCESS            0x40
 704 #define K7_DATA_CACHE_MISS              0x41
 705 #define K7_DATA_CACHE_REFILL            0x42
 706 #define K7_DATA_CACHE_REFILL_SYSTEM     0x43
 707 #define K7_DATA_CACHE_WBACK             0x44
 708 #define K7_L2_DTLB_HIT                  0x45
 709 #define K7_L2_DTLB_MISS                 0x46
 710 #define K7_MISALIGNED_DATA_REF          0x47
 711 #define K7_SYSTEM_REQUEST               0x64
 712 #define K7_SYSTEM_REQUEST_TYPE          0x65
 713
 714 #define K7_SNOOP_HIT                    0x73
 715 #define K7_SINGLE_BIT_ECC_ERROR         0x74
 716 #define K7_CACHE_LINE_INVAL             0x75
 717 #define K7_CYCLES_PROCESSOR_IS_RUNNING  0x76
 718 #define K7_L2_REQUEST                   0x79
 719 #define K7_L2_REQUEST_BUSY              0x7a
 720
 721 /* Instruction Fetch Unit */
 722 #define K7_IFU_IFETCH                   0x80
 723 #define K7_IFU_IFETCH_MISS              0x81
 724 #define K7_IFU_REFILL_FROM_L2           0x82
 725 #define K7_IFU_REFILL_FROM_SYSTEM       0x83
 726 #define K7_ITLB_L1_MISS                 0x84
 727 #define K7_ITLB_L2_MISS                 0x85
 728 #define K7_SNOOP_RESYNC                 0x86
 729 #define K7_IFU_STALL                    0x87
 730
 731 #define K7_RETURN_STACK_HITS            0x88
 732 #define K7_RETURN_STACK_OVERFLOW        0x89
 733
 734 /* Retired */
 735 #define K7_RETIRED_INST                 0xc0
 736 #define K7_RETIRED_OPS                  0xc1
 737 #define K7_RETIRED_BRANCHES             0xc2
 738 #define K7_RETIRED_BRANCH_MISPREDICTED  0xc3
 739 #define K7_RETIRED_TAKEN_BRANCH         0xc4
 740 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED    0xc5
 741 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
 742 #define K7_RETIRED_RESYNC_BRANCH        0xc7
 743 #define K7_RETIRED_NEAR_RETURNS         0xc8
 744 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED    0xc9
 745 #define K7_RETIRED_INDIRECT_MISPREDICTED        0xca
 746
 747 /* Interrupts */
 748 #define K7_CYCLES_INT_MASKED            0xcd
 749 #define K7_CYCLES_INT_PENDING_AND_MASKED        0xce
 750 #define K7_HW_INTR_RECV                 0xcf
 751
 752 #define K7_INSTRUCTION_DECODER_EMPTY    0xd0
 753 #define K7_DISPATCH_STALLS              0xd1
 754 #define K7_BRANCH_ABORTS_TO_RETIRE      0xd2
 755 #define K7_SERIALIZE                    0xd3
 756 #define K7_SEGMENT_LOAD_STALL           0xd4
 757 #define K7_ICU_FULL                     0xd5
 758 #define K7_RESERVATION_STATIONS_FULL    0xd6
 759 #define K7_FPU_FULL                     0xd7
 760 #define K7_LS_FULL                      0xd8
 761 #define K7_ALL_QUIET_STALL              0xd9
 762 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING        0xda
 763
 764 #define K7_BP0_MATCH                    0xdc
 765 #define K7_BP1_MATCH                    0xdd
 766 #define K7_BP2_MATCH                    0xde
 767 #define K7_BP3_MATCH                    0xdf