sys/arch/x86/pci/amdtemp.c

   1 /*      $NetBSD: amdtemp.c,v 1.8 2009/06/16 07:34:40 cegger Exp $ */
   2 /*      $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $   */
   3
   4 /*
   5  * Copyright (c) 2008 The NetBSD Foundation, Inc.
   6  * All rights reserved.
   7  *
   8  * This code is derived from software contributed to The NetBSD Foundation
   9  * by Christoph Egger.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd@bugmail.mojo.ru>
  35  *
  36  * Permission to use, copy, modify, and distribute this software for any
  37  * purpose with or without fee is hereby granted, provided that the above
  38  * copyright notice and this permission notice appear in all copies.
  39  *
  40  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  41  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  42  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  43  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  44  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  45  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  46  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  47  */
  48
  49
  50 #include <sys/cdefs.h>
  51 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.8 2009/06/16 07:34:40 cegger Exp $ ");
  52
  53 #include <sys/param.h>
  54 #include <sys/systm.h>
  55 #include <sys/device.h>
  56 #include <sys/kmem.h>
  57 #include <dev/sysmon/sysmonvar.h>
  58
  59 #include <sys/bus.h>
  60 #include <sys/cpu.h>
  61 #include <machine/specialreg.h>
  62
  63 #include <dev/pci/pcireg.h>
  64 #include <dev/pci/pcivar.h>
  65 #include <dev/pci/pcidevs.h>
  66
  67 /*
  68  * AMD K8:
  69  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
  70  * AMD K8 Errata: #141
  71  * http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf
  72  *
  73  * Family10h:
  74  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF
  75  * Family10h Errata: #319
  76  * http://support.amd.com/de/Processor_TechDocs/41322.pdf
  77  *
  78  * Family11h:
  79  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf
  80  */
  81
  82 /* AMD Proessors, Function 3 -- Miscellaneous Control
  83  */
  84
  85 /* Function 3 Registers */
  86 #define THERMTRIP_STAT_R      0xe4
  87 #define NORTHBRIDGE_CAP_R     0xe8
  88 #define CPUID_FAMILY_MODEL_R  0xfc
  89
  90 /*
  91  * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control
  92  */
  93
  94 /* Bits within Thermtrip Status Register */
  95 #define K8_THERM_SENSE_SEL       (1 << 6)
  96 #define K8_THERM_SENSE_CORE_SEL  (1 << 2)
  97
  98 /* Flip core and sensor selection bits */
  99 #define K8_T_SEL_C0(v)           (v |= K8_THERM_SENSE_CORE_SEL)
 100 #define K8_T_SEL_C1(v)           (v &= ~(K8_THERM_SENSE_CORE_SEL))
 101 #define K8_T_SEL_S0(v)           (v &= ~(K8_THERM_SENSE_SEL))
 102 #define K8_T_SEL_S1(v)           (v |= K8_THERM_SENSE_SEL)
 103
 104
 105
 106 /*
 107  * AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control
 108  */
 109
 110 /* Function 3 Registers */
 111 #define F10_TEMPERATURE_CTL_R   0xa4
 112
 113 /* Bits within Reported Temperature Control Register */
 114 #define F10_TEMP_CURTEMP        (1 << 21)
 115
 116 /*
 117  * Revision Guide for AMD NPT Family 0Fh Processors,
 118  * Publication # 33610, Revision 3.30, February 2008
 119  */
 120 #define K8_SOCKET_F     1       /* Server */
 121 #define K8_SOCKET_AM2   2       /* Desktop */
 122 #define K8_SOCKET_S1    3       /* Laptop */
 123
 124 static const struct {
 125         const char      rev[5];
 126         const struct {
 127                 const pcireg_t  cpuid;
 128                 const uint8_t   socket;
 129         } cpu[5];
 130 } amdtemp_core[] = {
 131         { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 },      /* F2 */
 132                   { 0x00040F80, K8_SOCKET_S1 },         /* F2 */
 133                   { 0, 0 }, { 0, 0 }, { 0, 0 } } },
 134         { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 },      /* F2 */
 135                   { 0x00040FC0, K8_SOCKET_S1 },         /* F2 */
 136                   { 0x00050FF0, K8_SOCKET_AM2 },        /* F2, F3 */
 137                   { 0, 0 }, { 0, 0 } } },
 138         { "JH-F", { { 0x00040F10, K8_SOCKET_F },        /* F2, F3 */
 139                   { 0x00040F30, K8_SOCKET_AM2 },        /* F2, F3 */
 140                   { 0x000C0F10, K8_SOCKET_F },          /* F3 */
 141                   { 0, 0 }, { 0, 0 } } },
 142         { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 },      /* G1, G2 */
 143                   { 0x00060F80, K8_SOCKET_S1 },         /* G1, G2 */
 144                   { 0, 0 }, { 0, 0 }, { 0, 0 } } },
 145         { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 },      /* G1, G2 */
 146                   { 0x00060FC0, K8_SOCKET_S1 },         /* G2 */
 147                   { 0x00070FF0, K8_SOCKET_AM2 },        /* G1, G2 */
 148                   { 0x00070FC0, K8_SOCKET_S1 },         /* G2 */
 149                   { 0, 0 } } }
 150 };
 151
 152
 153 struct amdtemp_softc {
 154         pci_chipset_tag_t sc_pc;
 155         pcitag_t sc_pcitag;
 156
 157         struct sysmon_envsys *sc_sme;
 158         envsys_data_t *sc_sensor;
 159
 160         char sc_rev;
 161         int8_t sc_numsensors;
 162         uint32_t sc_family;
 163         int32_t sc_adjustment;
 164 };
 165
 166
 167 static int amdtemp_match(device_t, cfdata_t, void *);
 168 static void amdtemp_attach(device_t, device_t, void *);
 169
 170 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t);
 171 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int);
 172 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *);
 173
 174 static void amdtemp_family10_init(struct amdtemp_softc *);
 175 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int);
 176 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *);
 177
 178 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc),
 179         amdtemp_match, amdtemp_attach, NULL, NULL);
 180
 181 static int
 182 amdtemp_match(device_t parent, cfdata_t match, void *aux)
 183 {
 184         struct pci_attach_args *pa = aux;
 185         pcireg_t cpu_signature;
 186         uint32_t family;
 187
 188         if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
 189                 return 0;
 190
 191         switch (PCI_PRODUCT(pa->pa_id)) {
 192         case PCI_PRODUCT_AMD_AMD64_MISC:
 193         case PCI_PRODUCT_AMD_AMD64_F10_MISC:
 194         case PCI_PRODUCT_AMD_AMD64_F11_MISC:
 195                 break;
 196         default:
 197                 return 0;
 198         }
 199
 200         cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag,
 201                                 CPUID_FAMILY_MODEL_R);
 202
 203         /* This CPUID northbridge register has been introduced
 204          * in Revision F */
 205         if (cpu_signature == 0x0)
 206                 return 0;
 207
 208         family = CPUID2FAMILY(cpu_signature);
 209         if (family == 0xf)
 210                 family += CPUID2EXTFAMILY(cpu_signature);
 211
 212         /* Errata #319: This has been fixed in Revision C2. */
 213         if (family == 0x10) {
 214                 if (CPUID2MODEL(cpu_signature) < 4)
 215                         return 0;
 216                 if (CPUID2MODEL(cpu_signature) == 4
 217                     && CPUID2STEPPING(cpu_signature) < 2)
 218                         return 0;
 219         }
 220
 221
 222         /* Not yet supported CPUs */
 223         if (family >= 0x12)
 224                 return 0;
 225
 226         return 2;       /* supercede pchb(4) */
 227 }
 228
 229 static void
 230 amdtemp_attach(device_t parent, device_t self, void *aux)
 231 {
 232         struct amdtemp_softc *sc = device_private(self);
 233         struct pci_attach_args *pa = aux;
 234         pcireg_t cpu_signature;
 235         size_t len;
 236         int error;
 237         uint8_t i;
 238
 239         aprint_naive("\n");
 240         aprint_normal(": AMD CPU Temperature Sensors");
 241
 242         cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag,
 243                                 CPUID_FAMILY_MODEL_R);
 244
 245         /* If we hit this, then match routine is wrong. */
 246         KASSERT(cpu_signature != 0x0);
 247
 248         sc->sc_family = CPUID2FAMILY(cpu_signature)
 249                 + CPUID2EXTFAMILY(cpu_signature);
 250         KASSERT(sc->sc_family >= 0xf);
 251
 252         sc->sc_pc = pa->pa_pc;
 253         sc->sc_pcitag = pa->pa_tag;
 254         sc->sc_adjustment = 0;
 255
 256         switch (sc->sc_family) {
 257         case 0xf:  /* AMD K8 NPT */
 258                 amdtemp_k8_init(sc, cpu_signature);
 259                 break;
 260
 261         case 0x10: /* AMD Barcelona/Phenom */
 262         case 0x11: /* AMD Griffin */
 263                 amdtemp_family10_init(sc);
 264                 break;
 265
 266         default:
 267                 aprint_normal(", family 0x%x not supported\n",
 268                              sc->sc_family);
 269                 return;
 270         }
 271
 272         aprint_normal("\n");
 273
 274         if (sc->sc_adjustment != 0)
 275                 aprint_debug_dev(self, "Workaround enabled\n");
 276
 277         sc->sc_sme = sysmon_envsys_create();
 278         len = sizeof(envsys_data_t) * sc->sc_numsensors;
 279         sc->sc_sensor = kmem_zalloc(len, KM_NOSLEEP);
 280         if (!sc->sc_sensor)
 281                 goto bad2;
 282
 283         switch (sc->sc_family) {
 284         case 0xf:
 285                 amdtemp_k8_setup_sensors(sc, device_unit(self));
 286                 break;
 287         case 0x10:
 288         case 0x11:
 289                 amdtemp_family10_setup_sensors(sc, device_unit(self));
 290                 break;
 291         }
 292
 293         /*
 294          * Set properties in sensors.
 295          */
 296         for (i = 0; i < sc->sc_numsensors; i++) {
 297                 if (sysmon_envsys_sensor_attach(sc->sc_sme,
 298                                                 &sc->sc_sensor[i]))
 299                         goto bad;
 300         }
 301
 302         /*
 303          * Register the sysmon_envsys device.
 304          */
 305         sc->sc_sme->sme_name = device_xname(self);
 306         sc->sc_sme->sme_cookie = sc;
 307
 308         switch (sc->sc_family) {
 309         case 0xf:
 310                 sc->sc_sme->sme_refresh = amdtemp_k8_refresh;
 311                 break;
 312         case 0x10:
 313         case 0x11:
 314                 sc->sc_sme->sme_refresh = amdtemp_family10_refresh;
 315                 break;
 316         }
 317
 318         error = sysmon_envsys_register(sc->sc_sme);
 319         if (error) {
 320                 aprint_error_dev(self, "unable to register with sysmon "
 321                         "(error=%d)\n", error);
 322                 goto bad;
 323         }
 324
 325         if (!pmf_device_register(self, NULL, NULL))
 326                 aprint_error_dev(self, "couldn't establish power handler\n");
 327
 328         return;
 329
 330 bad:
 331         kmem_free(sc->sc_sensor, len);
 332 bad2:
 333         sysmon_envsys_destroy(sc->sc_sme);
 334 }
 335
 336 static void
 337 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature)
 338 {
 339         pcireg_t data;
 340         uint32_t cmpcap;
 341         uint8_t i, j;
 342
 343         aprint_normal(" (K8");
 344
 345         for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) {
 346                 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) {
 347                         if ((cpu_signature & ~0xf)
 348                             != amdtemp_core[i].cpu[j].cpuid)
 349                                 continue;
 350
 351                         sc->sc_rev = amdtemp_core[i].rev[3];
 352                         aprint_normal(": core rev %.4s%.1x",
 353                                 amdtemp_core[i].rev,
 354                                 CPUID2STEPPING(cpu_signature));
 355
 356                         switch (amdtemp_core[i].cpu[j].socket) {
 357                         case K8_SOCKET_AM2:
 358                                 if (sc->sc_rev == 'G')
 359                                         sc->sc_adjustment = 21000000;
 360                                 aprint_normal(", socket AM2");
 361                                 break;
 362                         case K8_SOCKET_S1:
 363                                 aprint_normal(", socket S1");
 364                                 break;
 365                         case K8_SOCKET_F:
 366                                 aprint_normal(", socket F");
 367                                 break;
 368                         }
 369                 }
 370         }
 371
 372         if (sc->sc_rev == '\0') {
 373                 /* CPUID Family Model Register was introduced in
 374                  * Revision F */
 375                 sc->sc_rev = 'G';       /* newer than E, assume G */
 376                 aprint_normal(": cpuid 0x%x", cpu_signature);
 377         }
 378
 379         aprint_normal(")");
 380
 381         data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R);
 382         cmpcap = (data >> 12) & 0x3;
 383
 384         sc->sc_numsensors = cmpcap ? 4 : 2;
 385 }
 386
 387
 388 static void
 389 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit)
 390 {
 391         uint8_t i;
 392
 393         /* There are two sensors per CPU core. So we use the
 394          * device unit as socket counter to correctly enumerate
 395          * the CPUs on multi-socket machines.
 396          */
 397         dv_unit *= (sc->sc_numsensors / 2);
 398         for (i = 0; i < sc->sc_numsensors; i++) {
 399                 sc->sc_sensor[i].units = ENVSYS_STEMP;
 400                 sc->sc_sensor[i].state = ENVSYS_SVALID;
 401
 402                 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc),
 403                         "CPU%u Sensor%u", dv_unit + (i / 2), i % 2);
 404         }
 405 }
 406
 407
 408 static void
 409 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
 410 {
 411         struct amdtemp_softc *sc = sme->sme_cookie;
 412         pcireg_t status, match, tmp;
 413         uint32_t value;
 414
 415         status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R);
 416
 417         switch(edata->sensor) { /* sensor number */
 418         case 0: /* Core 0 Sensor 0 */
 419                 K8_T_SEL_C0(status);
 420                 K8_T_SEL_S0(status);
 421                 break;
 422         case 1: /* Core 0 Sensor 1 */
 423                 K8_T_SEL_C0(status);
 424                 K8_T_SEL_S1(status);
 425                 break;
 426         case 2: /* Core 1 Sensor 0 */
 427                 K8_T_SEL_C1(status);
 428                 K8_T_SEL_S0(status);
 429                 break;
 430         case 3: /* Core 1 Sensor 1 */
 431                 K8_T_SEL_C1(status);
 432                 K8_T_SEL_S1(status);
 433                 break;
 434         }
 435
 436         match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL);
 437         pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status);
 438         status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R);
 439         tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL);
 440
 441         value = 0x3ff & (status >> 14);
 442         if (sc->sc_rev != 'G')
 443                 value &= ~0x3;
 444
 445         edata->state = ENVSYS_SINVALID;
 446         if ((tmp == match) && ((value & ~0x3) != 0)) {
 447                 edata->state = ENVSYS_SVALID;
 448                 edata->value_cur = (value * 250000 - 49000000) + 273150000
 449                         + sc->sc_adjustment;
 450         }
 451 }
 452
 453
 454 static void
 455 amdtemp_family10_init(struct amdtemp_softc *sc)
 456 {
 457         aprint_normal(" (Family10h / Family11h)");
 458
 459         sc->sc_numsensors = 1;
 460 }
 461
 462 static void
 463 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit)
 464 {
 465         /* sanity check for future enhancements */
 466         KASSERT(sc->sc_numsensors == 1);
 467
 468         /* There's one sensor per memory controller (= socket)
 469          * so we use the device unit as socket counter
 470          * to correctly enumerate the CPUs
 471          */
 472         sc->sc_sensor[0].units = ENVSYS_STEMP;
 473         sc->sc_sensor[0].state = ENVSYS_SVALID;
 474
 475         snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc),
 476                 "CPU%u Sensor0", dv_unit);
 477 }
 478
 479
 480 static void
 481 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
 482 {
 483         struct amdtemp_softc *sc = sme->sme_cookie;
 484         pcireg_t status;
 485         uint32_t value;
 486
 487         status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, F10_TEMPERATURE_CTL_R);
 488
 489         value = (status >> 21);
 490
 491         edata->state = ENVSYS_SVALID;
 492         /* envsys(4) wants uK... convert from Celsius. */
 493         edata->value_cur = (value * 125000) + 273150000;
 494 }